Abstract: Device driven transfer of data from the device to a memory of a host. The device may receive data from one or more data sources. The device may transfer at least a portion of the data to the memory of the host coupled to the device. Transferring may be performed without an initiation of the transfer by the host. Additionally, transferring may include, for each of the one or more data sources, determining a portion of the memory medium corresponding to the data source, determining a latest value for the data source from the data, and storing the latest value for the data source in the portion of the memory. Storing the latest value may include overwriting a previous value of the data source when the previous value exists in the portion of the memory medium.

Abstract: Device driven transfer of data from the device to a memory of a host. The device may receive data from one or more data sources. The device may transfer at least a portion of the data to the memory of the host coupled to the device. Transferring may be performed without an initiation of the transfer by the host. Additionally, transferring may include, for each of the one or more data sources, determining a portion of the memory medium corresponding to the data source, determining a latest value for the data source from the data, and storing the latest value for the data source in the portion of the memory. Storing the latest value may include overwriting a previous value of the data source when the previous value exists in the portion of the memory medium.

Abstract: In some embodiments, a user may select an elemental function such as read, write, or configuration from a graphical programming environment. A file may be created that instantiates functionality into a programmable hardware element to allow it to send a command across a serial protocol to peripheral interface circuitry and ultimately to peripheral chips (e.g., network chips on a CAN). The elemental node concept may be generic to any network chip because the node may contain only the general data of a packet (e.g., command type, value of data bytes, etc). The actual interface to a network chip may be handled inside the peripheral interface circuitry. The peripheral interface circuitry may have the details of the network chip in which it interfaces and may abstract details of the network chip from the target programmable hardware element through the serial protocol.

Abstract: A system for interfacing a host computer to a Controller Area Network (CAN) bus. The system comprises a memory, an embedded processor and interface logic. The memory stores program code. The embedded processor couples to the memory and executes the program code. The interface logic interfaces the embedded processor with an interconnecting bus, e.g., the Real-Time System Integration (RTSI) bus. In response to execution of the program code, the embedded processor is operable to perform a CAN event in response to the interface logic receiving a RTSI trigger signal on a selected line of the RTSI bus. A peripheral device also coupled to the host computer assert the trigger signal in response to the peripheral device receiving and/or transmitting data. Furthermore, the interface logic is configured to assert a RTSI trigger signal on a selected line of said RTSI bus in response to the embedded processor performing a CAN event. CAN events include transmission/reception of a CAN frame.

Abstract: An improved dual-connector cable for connecting a computer to a serial instrumentation bus. In one embodiment, the serial instrumentation bus is a fieldbus, preferably either a Foundation fieldbus or a Controller Area Network (CAN) bus. The cable comprises a first terminal located at a first end of the cable for coupling the cable to the computer. The first terminal comprises a device connector which is configured to connect the first terminal to a connector on the computer. The cable also comprises a second terminal located at a second end of the cable for coupling the cable to the serial instrumentation bus. The second terminal comprises interface circuitry for interfacing the cable with the serial instrumentation bus. The second terminal further comprises a first bus connector that is electrically coupled to the serial instrumentation interface circuitry. The first bus connector is configured to connect to a mating connector for coupling to the serial instrumentation bus.