Patents by Inventor William R. Wheeler

William R. Wheeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11237840
    Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Amit Kumar, Chengda Yang, Aaron Gorius, William R. Wheeler
  • Patent number: 10922148
    Abstract: Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Myles Wilde, William R. Wheeler, Michael F. Fallon, Aaron Gorius, Amit Kumar, Chengda Yang
  • Publication number: 20200326955
    Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 15, 2020
    Inventors: Matthew J. Adiletta, Myles Wilde, Michael F. Fallon, Amit Kumar, Chengda Yang, Aaron Gorius, William R. Wheeler
  • Patent number: 10761979
    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
  • Publication number: 20200082782
    Abstract: Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Myles Wilde, Matthew J. Adiletta, William R. Wheeler, Michael F. Fallon, Thomas M. Garrison, Aaron Gorius, Chengda Yang
  • Publication number: 20190121682
    Abstract: Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.
    Type: Application
    Filed: April 26, 2016
    Publication date: April 25, 2019
    Inventors: Matthew J. Adiletta, Myles Wilde, William R. Wheeler, Michael F. Fallon, Aaron Gorius, Amit Kumar, Chengda Yang
  • Publication number: 20190027111
    Abstract: Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 24, 2019
    Applicant: Intel Corporation
    Inventors: MYLES WILDE, MATTHEW J. ADILETTA, WILLIAM R. WHEELER, MICHAEL F. FALLON, THOMAS M. GARRISON, AARON GORIUS, CHENGDA YANG
  • Patent number: 10032431
    Abstract: Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Myles Wilde, Matthew J. Adiletta, William R. Wheeler, Michael F. Fallon, Thomas M. Garrison, Aaron Gorius, Chengda Yang
  • Publication number: 20180095892
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Shirish Aundhe, Sandhya Viswanathan, David A. Koufaty
  • Publication number: 20180004655
    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
  • Publication number: 20160027399
    Abstract: Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.
    Type: Application
    Filed: March 13, 2014
    Publication date: January 28, 2016
    Applicant: INTEL CORPORATION
    Inventors: Matthew ADILETTA, Myles WILDE, Michael F. FALLON, William R. WHEELER, Thomas GARRISON, Aaron GORIUS, Chengda YANG
  • Patent number: 8316191
    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: William R. Wheeler, Bradley Burres, Matthew J. Adiletta, Gilbert Wolrich
  • Patent number: 7991983
    Abstract: A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Matthew J Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper
  • Patent number: 7911811
    Abstract: A switching power supply with the increased efficiency at light load has a switching power circuit, a power monitoring circuit and a light load power supplying circuit. The switching power circuit converts an AC power to a stable DC power and sends the DC power to a load according to voltage variation of the load. When the power monitoring circuit detects the AC power and determines that the load is in a light state, the power monitoring circuit controls the light load power supplying circuit to output a small-power DC to the load. As the DC power provided by the light load power supplying circuit is small, the switching loss ratio is lower in its light load state. Therefore, the operating efficiency at the light load state is higher.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: March 22, 2011
    Assignee: Acbel Polytech Inc.
    Inventors: William R. Wheeler, Wei-Liang Lin
  • Patent number: 7743235
    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: June 22, 2010
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Matthew Adiletta, William R. Wheeler
  • Publication number: 20090315409
    Abstract: A digital automatic monitoring and power breaking safety socket has a shell in which an electrical connection base is mounted for connecting to a power line and an external line plug inside. A power switch is connected in series between the electrical connection base and the power line. A digital power monitoring circuit is coupled to the power line detect the power status to control the power switch based on the power status. Further, a power line data communication circuit is mounted in the shell and connects to the digital power monitoring circuit to obtain and process the power status. The processed power status is loaded into the power line that connects to the electrical connection base. Therefore, in addition to automatic power breaking and supplying, a remote power management host is able to obtain the power status and remotely control the socket.
    Type: Application
    Filed: January 29, 2009
    Publication date: December 24, 2009
    Applicant: ACBEL POLYTECH INC.
    Inventors: William R. Wheeler, Chien-Long Lin, Shiann-Chang Yeh, Chien-Hong Lin, Che-Cheng Chang
  • Publication number: 20090307469
    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 10, 2009
    Applicant: Intel Corporation
    Inventors: Gilbert Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper
  • Publication number: 20090290387
    Abstract: A switching power supply with the increased efficiency at light load has a switching power circuit, a power monitoring circuit and a light load power supplying circuit. The switching power circuit converts an AC power to a stable DC power and sends the DC power to a load according to voltage variation of the load. When the power monitoring circuit detects the AC power and determines that the load is in a light state, the power monitoring circuit controls the light load power supplying circuit to output a small-power DC to the load. As the DC power provided by the light load power supplying circuit is small, the switching loss ratio is lower in its light load state. Therefore, the operating efficiency at the light load state is higher.
    Type: Application
    Filed: October 7, 2008
    Publication date: November 26, 2009
    Inventors: William R. Wheeler, Wei-Liang Lin
  • Patent number: 7546444
    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD—3 . . . THREAD—0). The processor maintains execution threads (THREAD—3 . . . THREAD—0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD—3 . . . THREAD—0).
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: June 9, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper
  • Patent number: 7532318
    Abstract: In one embodiment, a system to measure defects on a surface of a wafer and an edge of the wafer using a single tool comprises a radial motor to move an optical head in a radial direction to detect defects at locations displaced from the edge of the wafer, and a rotational motor to rotate the optical head around the edge of the wafer to detect defects on the edge of the wafer.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: May 12, 2009
    Assignee: KLA-Tencor Corporation
    Inventors: Steven W. Meeks, Rusmin Kudinar, William R. Wheeler, Hung Phi Nguyen, Vamsi Velidandla, Anoop Somanchi, Ronny Soetarman