Abstract: A class AB amplifier having an output stage comprising complementary common source transistors (T1, T2) has means for setting the quiescent current. These comprise a bias resistor (R1) through which a bias current is passed and which is connected between the gates of transistors (T1 and T2) to set their voltages. The current through the bias resistor (R1) is derived from two reference transistors (T3 and T4) which each have the desired quiescent current passed through them by current sources (3, 5). The gate voltages of the reference transistors (T3, T4) are applied across a reference resistor (R2) and the current through the reference resistor (R2) is mirrored (T5 to T9) to the bias resistor (R1).

Abstract: Apparatus for generating estimates of valid input signal values at sampling instants comprises a first data slicer (3) for slicing the input signal at a given level, data sequence detectors (205, 207) for detecting given data sequences in the input signal, second (301) and third (302) data slicers for slicing the input signal at signal values estimated for a given data bit of the given data sequences, memory elements (303, 304, 305; 306, 307, 308) for storing the outputs of the second (301) and third (302) data slicers when slicing the given data bit, and incrementing means (309, 311; 310, 312) for increasing or decreasing the estimated values depending on whether the stored outputs indicate the input signal value was above or below the estimated value when the given data bit was sliced by the second (301) or third (302) data slicer.

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k-1), pmb (k-1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline.

Abstract: A peak detector comprises a device for storing a value representing the currently detected peak amplitude (Cp,Cn), a circuit for detecting whether the input signal amplitude exceeds the stored value (D1 to D4), an apparatus for updating the stored value at a fast rate if the input signal amplitude exceeds the stored value by more than a given value (D1/V1, D3/V4), and an apparatus for updating the stored value at a slow rate if the input signal amplitude exceeds the stored value by less than the given value (D2/R2, D3/R3). Analogue and digital versions are described together with their application to data slicers in, for example, teletext decoders.

Abstract: A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).

Abstract: An amplifier, particularly a CMOS amplifier has a differential input which is fed to six differential pairs. The outputs of the first and third differential pair are combined and fed to inputs of a summing network, while the outputs of the fourth and fifth are combined and fed to inputs of the summing network. The second and sixth differential pairs are arranged to cancel the tail currents of the fifth and third pairs, respectively, when all of the devices are in their active state. Thus, regardless of the common mode input level with respect to the supply rails the output current is provided by four devices giving a constant g.sub.m and slew rate.

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: A vibration sensor for measuring the flow of vibrational energy through a structure comprises four accelerometers (24-27) placed in cruciform arrangement on the surface of the structure. The signals from the accelerometers are processed in pairs using sum/difference amplifiers (36-40) to give two rotational (41, 42) and one translational (43) acceleration signal. The acceleration signals are frequency modulated (46-48) by as local oscillator (53) of preselected frequency, low-pass filtered (62-64) and the rotational acceleration signals (68, 70) then multiplied (72, 73) in phase quadrature (54) with the translational acceleration signal (69). The DC components of the resulting signals (76) are proportional to the time-average vibrational power flow. Knowledge of the flow paths facilitates the design of the structure to minimize effects of unwanted vibrations.