Patents by Inventor William Richard Lawrence

William Richard Lawrence has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040015338
    Abstract: The present invention is directed to a method and apparatus for simulating digital electronic systems. The signal integrity of a digital electronic system is assessed by analyzing traces (e.g. wires between components) for cross coupling. Problem areas are identified by monitoring storage components or output ports of the electronic system. Wires (traces), which carry signal transitions to the storage component or output ports are analyzed and quantified based on timing windows associated with the wires (traces). The clock transitions into a storage device are analyzed and vulnerability windows are identified for the storage device. The vulnerability windows are time periods when cross coupling may occur on a storage device. If a timing window overlaps a vulnerability window the timing window is considered a critical timing window. Devices driving the transition on wires with critical timing windows are then analyzed.
    Type: Application
    Filed: July 19, 2002
    Publication date: January 22, 2004
    Inventors: William Richard Lawrence, Francisco A. Ostojic, Michael Rogers Lambert, Robert J. Martin, Edward V. Weber
  • Publication number: 20040015737
    Abstract: A method of characterizing and simulating electronic systems for signal integrity is presented. Each device in the electronic system is associated with at least one vulnerability table and at least one vulnerability window. The vulnerability table is a three dimensional table that characterizes the operation of the device and includes line length on one axis, coupling efficiency on another axis and drivers size of a gate, on the third axis. In addition a number of vulnerability windows are presented. The vulnerability window is a time period when a storage device may store the wrong data because of signal integrity issues in the electronic system. A vulnerability window is developed for each input to a storage device in the system. In addition a vulnerability window is developed based on a number of failure mechanisms used to characterize the system. Lastly, a mapped vulnerability window is presented for devices such as logical gates, which provide input to the storage device.
    Type: Application
    Filed: July 19, 2002
    Publication date: January 22, 2004
    Inventors: Robert J. Martin, William Richard Lawrence, Francisco A. Ostojic, Mark E. Hammer, Michael Rogers Lambert, Edward V. Weber
  • Patent number: 6392423
    Abstract: The present invention is directed to a method and apparatus for testing integrated circuit package devices using automatic testing equipment. The automatic testing equipment may be provided with a light source to enable the testing of image capture type integrated circuit devices. Alternatively, the automatic testing equipment may be provided with an imaging device, e.g., a camera, or both an imaging device and a light source to additionally enable the testing of display type integrated circuit devices.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: May 21, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Bradley D. Pace, Durbin L. Seidel, William Richard Lawrence
  • Publication number: 20010019275
    Abstract: The present invention is directed to a method and apparatus for testing integrated circuit package devices using automatic testing equipment. The automatic testing equipment may be provided with a light source to enable the testing of image capture type integrated circuit devices. Alternatively, the automatic testing equipment may be provided with an imaging device, e.g., a camera, or both an imaging device and a light source to additionally enable the testing of display type integrated circuit devices.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 6, 2001
    Inventors: Bradley D. Pace, Durbin L. Seidel, William Richard Lawrence
  • Patent number: 6285200
    Abstract: The present invention is directed to a method and apparatus for testing integrated circuit package devices using automatic testing equipment. The automatic testing equipment may be provided with a light source to enable the testing of image capture type integrated circuit devices. Alternatively, the automatic testing equipment may be provided with an imaging device, e.g., a camera, or both an imaging device and a light source to additionally enable the testing of display type integrated circuit devices.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: September 4, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Bradley D. Pace, Durbin L. Seidel, William Richard Lawrence
  • Patent number: 6219443
    Abstract: The present invention provides a method and apparatus for detecting defects in a display. The apparatus of the present invention comprises a camera for capturing an image of a display being inspected and processing circuitry, such as, for example, a microprocessor or a digital signal processor (DSP), for processing the captured image to determine whether or not the display being inspected is defective. Preferably, the processing circuitry is a microprocessor running image processing software which controls data acquisition as well as the processing of the acquired data to determine whether the display being inspected is defective. In accordance with the present invention, a relatively high resolution display can be inspected using a single camera, preferably a charge-coupled device (CCD) camera, which has a lower resolution than the display being inspected. The camera is focused on the display such that the entire display is within the field of view of the camera.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: April 17, 2001
    Assignee: Agilent Technologies, Inc.
    Inventor: William Richard Lawrence