Patents by Inventor William Ring
William Ring has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240342497Abstract: A method of treating a subject that includes positioning a plurality of magnetic sources in proximity to a head of the subject, each magnetic source being configured to provide a magnetic field, selecting a phase offset between a first magnetic field provided by a first magnetic source of the plurality of magnetic sources and a second magnetic field provided by a second magnetic source of the plurality of magnetic sources, operating the plurality of magnetic sources with the selected phase offset, and applying the magnetic fields provided by the plurality of magnetic sources to the head of the subject to provide a therapeutic treatment within a target area of the subject's brain, wherein the magnetic fields combine to produce a rotating magnetic field vector in proximity to the target area of the subject's brain.Type: ApplicationFiled: April 17, 2024Publication date: October 17, 2024Inventors: James William Phillips, Robert Isenhart, Alexander Joseph Ring
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Publication number: 20240338399Abstract: Disclosed are examples of a system, techniques and non-transitory computer-readable storage medium that enable the selection of a response document template for generating an appropriate response to notification document. Respective components may generate an electronic document from the notification document. A common theme between two or more of the electronic documents may be identified. The electronic documents identified as having the common theme may be grouped in a notification document corpus. The notification document corpus may be analyzed with reference to received notification documents stored in a document repository. Based on results of the analysis, a template of a notification response document appropriate for responding to a specific notification document received by the enterprise may be selected. The selected response document template may be forwarded to a client device for further processing.Type: ApplicationFiled: December 22, 2023Publication date: October 10, 2024Applicant: Capital One Services, LLCInventors: Joerg RINGS, William Thomas ROMANO, Andre GATORANO
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Publication number: 20240329310Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Patent number: 12092378Abstract: Generally, management of refrigerant in an evaporator of an HVAC chiller is described. Methods, systems, and apparatuses to manage refrigerant in an evaporator can include one or combination of the following approaches: (1) by use of a refrigerant displacement array to physically prevent refrigerant from residing where the array is positioned (2) by control of the interstitial velocity of refrigerant flow within the volume of the shell of an evaporator; (3) by a phase biased distribution of the refrigerant mixture, so that a gaseous portion is uniformly distributed into the evaporator shell, while liquid refrigerant and oil is distributed into the evaporator shell at a designated area; and (4) by preventing or reducing the occurrence of foaming inside the evaporator through anti-foaming surfaces, such as by the use of refrigerant phobic and lubricant phobic material(s). Refrigerant management can in turn improve the thermal performance and overall efficiency of the evaporator.Type: GrantFiled: December 7, 2020Date of Patent: September 17, 2024Assignee: TRANE INTERNATIONAL INC.Inventors: Jon Phillip Hartfield, Harry Kenneth Ring, Michael William Groen, Stephen Anthony Kujak, Ronald Maurice Cosby, II
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Patent number: 12007604Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: GrantFiled: January 3, 2023Date of Patent: June 11, 2024Assignee: POET Technologies, Inc.Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Patent number: 11867946Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400° C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: GrantFiled: December 26, 2022Date of Patent: January 9, 2024Assignee: POET Technologies, Inc.Inventors: William Ring, Miroslaw Florjanczyk
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Publication number: 20230152519Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: ApplicationFiled: January 3, 2023Publication date: May 18, 2023Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Publication number: 20230135231Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400° C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: ApplicationFiled: December 26, 2022Publication date: May 4, 2023Inventors: William Ring, Miroslaw Florjanczyk
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Patent number: 11573372Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: GrantFiled: March 29, 2021Date of Patent: February 7, 2023Inventors: William Ring, Suresh Venkatesan
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Patent number: 11543588Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: GrantFiled: October 25, 2021Date of Patent: January 3, 2023Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Patent number: 11536904Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: GrantFiled: April 19, 2021Date of Patent: December 27, 2022Inventors: William Ring, Miroslaw Florjanczyk
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Patent number: 11351791Abstract: A logic circuitry package includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit. The logic circuit is configured to receive, via the interface, a plurality of first requests in a heater disabled mode, each first request corresponding to a different sensor ID of a plurality of sensor IDs; transmit, via the interface, a first digital value in response to each first request; receive, via the interface, a plurality of second requests in a heater enabled mode, each second request corresponding to a different sensor ID of the plurality of sensor IDs; and transmit, via the interface, a second digital value in response to each second request. Delta values corresponding to a difference between the first digital value and the second digital value for each different sensor ID of the plurality of sensor IDs are indicative of a print material level.Type: GrantFiled: December 3, 2019Date of Patent: June 7, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: James Michael Gardner, James William Ring, David Owen Roethig, Christopher Hans Bakker
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Patent number: 11338586Abstract: This disclosure describes integrated circuits which may be provided in logic circuitry packages and/or replaceable print apparatus components with print material reservoirs. An integrated circuit or logic circuitry package for a replaceable print apparatus component comprises an interface to communicate with a print apparatus logic circuit and at least one logic circuit.Type: GrantFiled: December 3, 2019Date of Patent: May 24, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Anthony D. Studer, Quinton B. Weaver, David N. Olsen, James Michael Gardner, James William Ring, David Owen Roethig, Christopher Hans Bakker
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Publication number: 20220043210Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Patent number: 11156779Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.Type: GrantFiled: July 20, 2020Date of Patent: October 26, 2021Assignee: POET Technologies, Inc.Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
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Publication number: 20210255386Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: ApplicationFiled: April 19, 2021Publication date: August 19, 2021Inventors: William Ring, Miroslaw Florjanczyk
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Publication number: 20210215876Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: William Ring, Suresh Venkatesan
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Patent number: 10983277Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: GrantFiled: January 18, 2020Date of Patent: April 20, 2021Assignee: POET Technologies, Inc.Inventors: William Ring, Miroslaw Florjanczyk
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Patent number: 10962715Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.Type: GrantFiled: July 16, 2018Date of Patent: March 30, 2021Assignee: POET Technologies, Inc.Inventors: William Ring, Suresh Venkatesan
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Patent number: 10946665Abstract: In one example, a method for determining an out-of-liquid condition of a liquid supply for an inkjet printer. The method includes acquiring, during printing, a sequence of data points, each data point comprising a differential liquid/air pressure at the liquid supply measured with a sensor and a corresponding cumulative amount of liquid delivered from the liquid supply. The method further includes generating a curve using the data points. The method also includes determining, from a predetermined characteristic of the curve, whether the out-of-liquid condition exists. The characteristic is independent of at least one of a gain and an offset of the sensor.Type: GrantFiled: July 12, 2017Date of Patent: March 16, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Matthew Jason Janssen, James William Ring, James Ronald Cole