Patents by Inventor William Robert Flederbach

William Robert Flederbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170046278
    Abstract: Techniques and apparatus are provided for updating replacement policy information for a fully associative buffer cache. A method is provided that generally includes updating replacement policy information for entries in a second cache memory based on hits indicating corresponding set-matching entries are present in the first cache memory, and evicting entries from the second cache memory based on the updated replacement policy information.
    Type: Application
    Filed: March 29, 2016
    Publication date: February 16, 2017
    Inventors: Robert Douglas CLANCY, Gaurav MEHTA, Michael Scott MCILVAINE, William Robert FLEDERBACH
  • Patent number: 9413344
    Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer
  • Publication number: 20160072491
    Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
    Type: Application
    Filed: March 25, 2015
    Publication date: March 10, 2016
    Inventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer