Abstract: A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.

Abstract: A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU. In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller.

Abstract: A cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a switching mechanism for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a configuration mechanism for locking at least one of the plurality of slave buses in response to a transfer request initiated by a master device attached to one of the plurality of master buses. The cross-bar switch has the capability of selectively locking slave buses during a bus lock transfer. In the preferred embodiment, the configuration mechanism is a Bus Lock Bit on Configuration Registers on the cross-bar switch. The Bus Lock Bit is programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmable and changed by a processor in a larger system.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: The present invention provides a method and system for bypassing defective sections with a memory array of a computer chip. The circuit in accordance with the present invention includes a register for controlling the effective size of the memory array based upon the detection of at least one defective section in the memory array, and a multiplexer for receiving an index address for the memory array and for the mapping of the index address based upon the register means. The circuit in accordance with the present invention does not use fuses to conduct repairs and thus does not require additional area on the chip for such fuses. As such, it eliminates the complications in the manufacturing process related to fuses and redundant cells. The circuit in accordance with the present invention dynamically manipulates the address of the array to bypass the defective regions of the array.

Abstract: A variable clock generator includes a clock multiplier that generates from a reference clock at least two clock signals which are out of phase with each other and a clock divider which receives a plurality of divider patterns and which receives at least two clock signals from the clock multiplier. The clock divider generates an output clock based on the divider patterns and the clock signals. In a particular embodiment, the clock divider includes a plurality of loadable linear feedback shift registers each having an output. An EXCLUSIVE OR gate that is responsive to the outputs of the linear feedback shift registers then EXCLUSIVE ORs the outputs of the linear feedback shift registers to produce the output clock. Preferably, the size of the linear feedback shift registers corresponds to the size of the divider patterns.

Abstract: The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.

Abstract: A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing v

Abstract: The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.

Abstract: Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.

Abstract: A programmable memory controller includes a plurality of multi-bit registers, with each multi-bit register coupled to a cycle generator. Each cycle generator is formed from a multi-bit shift register and control signals which drive each multi-bit shift register so that data in an associated multi-bit register is shifted through the shift register to form desired memory control pulses.