Patents by Inventor William Robert Stoye

William Robert Stoye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250014259
    Abstract: A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 9, 2025
    Applicant: Arm Limited
    Inventors: Yoav Asher Levy, Jakob Axel Fries, William Robert Stoye
  • Publication number: 20240371076
    Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit when returning rays' processing to the programmable execution unit is operable to group rays together for continued execution by the programmable execution unit as a respective thread group.
    Type: Application
    Filed: March 26, 2024
    Publication date: November 7, 2024
    Applicant: Arm Limited
    Inventors: Richard Edward Bruce, William Robert Stoye, Jakob Axel Fries
  • Publication number: 20240371075
    Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit may need to stop a ray's traversal to return the ray's processing to the programmable execution unit before the ray's traversal is subsequently restarted. In that case, the ray's traversal is restarted from the beginning.
    Type: Application
    Filed: March 26, 2024
    Publication date: November 7, 2024
    Applicant: Arm Limited
    Inventors: Richard Edward Bruce, William Robert Stoye, Jakob Axel Fries, Wing-Tsi Henry Wong
  • Publication number: 20240371070
    Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray tracing circuit of the graphics processor may require additional storage space to store test record entries to trace a ray, additional storage space is allocated for the ray tracing circuit to use to store test record entries to trace the ray.
    Type: Application
    Filed: March 12, 2024
    Publication date: November 7, 2024
    Applicant: Arm Limited
    Inventors: Jakob Axel Fries, William Robert Stoye, Richard Edward Bruce
  • Patent number: 12106422
    Abstract: An instruction (or set of instructions) that can be included in a program to perform a ray tracing acceleration data structure traversal, with individual execution threads in a group of execution threads executing the program performing a traversal operation for a respective ray in a corresponding group of rays such that the group of rays performing the traversal operation together. The instruction(s), when executed by the execution threads in respect of a node of the ray tracing acceleration data structure, cause one or more rays from the group of plural rays that are performing the traversal operation together to be tested for intersection with the one or more volumes associated with the node being tested. A result of the ray-volume intersection testing can then be returned for the traversal operation.
    Type: Grant
    Filed: June 4, 2022
    Date of Patent: October 1, 2024
    Assignee: Arm Limited
    Inventors: Richard Bruce, William Robert Stoye, Mathieu Jean Joseph Robart
  • Patent number: 12067668
    Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: August 20, 2024
    Assignee: Arm Limited
    Inventors: Richard Bruce, William Robert Stoye, Mathieu Jean Joseph Robart, Jørn Nystad
  • Publication number: 20240169644
    Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information comprises the depth buffer.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Applicant: Arm Limited
    Inventors: Tord Kvestad Øygard, Sandeep Kakarlapudi, Toni Viki Brkic, William Robert Stoye
  • Publication number: 20240037692
    Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry including, inter alia, at least an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents, and an indication of whether the group of fragments that the list entry represents is eligible to undergo particular processing operations. The coverage information and eligibility information for the list entries is then used to control the processing of fragments for sub-regions of a tile, in such a way as to ensure that processing order dependencies are enforced and met.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 1, 2024
    Applicant: Arm Limited
    Inventors: William Robert Stoye, Olof Henrik Uhrenholt, Wing-Tsi Henry Wong, Edward Hardy, Toni Viki Brkic, Ole Magnus Ruud
  • Publication number: 20240037853
    Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 1, 2024
    Applicant: Arm Limited
    Inventors: William Robert Stoye, Olof Henrik Uhrenholt, Wing-Tsi Henry Wong, Edward Hardy, Toni Viki Brkic, Ole Magnus Ruud
  • Publication number: 20220392146
    Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 8, 2022
    Inventors: Richard Bruce, William Robert Stoye, Mathieu Jean Joseph Robart, Jørn Nystad
  • Patent number: 11442731
    Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 13, 2022
    Assignee: Arm Limited
    Inventors: John David Robson, Sean Tristram LeGuay Ellis, William Robert Stoye
  • Patent number: 11276137
    Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 15, 2022
    Assignee: Arm Limited
    Inventors: Isidoros Sideris, Stephane Forey, William Robert Stoye, John David Robson
  • Publication number: 20210157600
    Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Applicant: Arm Limited
    Inventors: Luka Dejanovic, William Robert Stoye
  • Patent number: 11016774
    Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Arm Limited
    Inventors: Luka Dejanovic, William Robert Stoye
  • Publication number: 20210117192
    Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Arm Limited
    Inventors: John David Robson, Sean Tristram LeGuay Ellis, William Robert Stoye
  • Patent number: 10891708
    Abstract: A shader program to be executed by a graphics processor has associated with it a start instruction indication, indicating the instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread, and includes a set-entry instruction, which, when executed by a thread, will cause the start instruction indication to be modified to indicate a different instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread. When executing the program, execution threads determine from the start instruction indication associated with the program, the instruction in the sequence of instructions for the program at which they should start execution of the program.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 12, 2021
    Assignee: Arm Limited
    Inventors: Sean Tristram LeGuay Ellis, William Robert Stoye
  • Patent number: 10290132
    Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 14, 2019
    Assignee: Arm Limited
    Inventors: William Robert Stoye, Samuel Martin
  • Patent number: 10157132
    Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 18, 2018
    Assignee: Arm Limited
    Inventors: Edvard Fielding, Andreas Due Engh-Halstvedt, Jorn Nystad, Antonio Garcia Guirado, William Robert Stoye, Ian Rudolf Bratt
  • Publication number: 20160284043
    Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.
    Type: Application
    Filed: March 21, 2016
    Publication date: September 29, 2016
    Applicant: ARM Limited
    Inventors: William Robert Stoye, Samuel Martin
  • Patent number: 7219315
    Abstract: Disclosed is a method of simulating semiconductor circuitry in which trace data received from a first simulation of the semiconductor circuitry, is processed and the values of inputs to the semiconductor circuitry read from the trace data are output to a second simulation of semiconductor circuitry. There is also disclosed a method of determining whether first and second simulations of semiconductor circuitry are equivalent in which transitions in the values of registers simulated by the first and second simulations are analysed, and an error is declared if, following a register in either simulation making a transition to a value which is not equivalent to the corresponding register in the other simulation. The value of the register in the same simulation makes a further transition to a non-equivalent value before the value of the register in the other simulation makes a transition to an equivalent value.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: May 15, 2007
    Assignee: Tenison Technology EDA Limited
    Inventors: William Robert Stoye, Robert Mark Alistair Murray