Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.

Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry including, inter alia, at least an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents, and an indication of whether the group of fragments that the list entry represents is eligible to undergo particular processing operations. The coverage information and eligibility information for the list entries is then used to control the processing of fragments for sub-regions of a tile, in such a way as to ensure that processing order dependencies are enforced and met.

Abstract: There is disclosed an instruction that can be included into a graphics processor shader program to be executed by a group of execution threads that when executed will cause a group of execution lanes to be in an ‘active’ (e.g. SIMD) execution state in which active state processing operations can be performed using the group of plural execution lanes together. The processing operations can then be performed using the execution lanes in the active state together. The execution lanes are then allowed or caused to return to their prior execution state once the processing operations have finished.

Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.

Abstract: An instruction (or set of instructions) that can be included in a program to perform a ray tracing acceleration data structure traversal, with individual execution threads in a group of execution threads executing the program performing a traversal operation for a respective ray in a corresponding group of rays such that the group of rays performing the traversal operation together. The instruction(s), when executed by the execution threads in respect of a node of the ray tracing acceleration data structure, cause one or more rays from the group of plural rays that are performing the traversal operation together to be tested for intersection with the one or more volumes associated with the node being tested. A result of the ray-volume intersection testing can then be returned for the traversal operation.

Abstract: An instruction, or set of instructions, that can be included in a program to perform a ray tracing acceleration data structure traversal, with individual execution threads in a group of execution threads executing the program performing a traversal operation for a respective ray in a corresponding group of rays such that the group of rays performing the traversal operation together. The instruction(s), when executed by the execution threads in respect of a node of the ray tracing acceleration data structure, cause one or more rays from the group of plural rays that are performing the traversal operation together to be tested for intersection with the one or more volumes associated with the node being tested. A result of the ray-volume intersection testing can then be returned for the traversal operation.

Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.

Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.

Abstract: A shader program to be executed by a graphics processor has associated with it a start instruction indication, indicating the instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread, and includes a set-entry instruction, which, when executed by a thread, will cause the start instruction indication to be modified to indicate a different instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread. When executing the program, execution threads determine from the start instruction indication associated with the program, the instruction in the sequence of instructions for the program at which they should start execution of the program.

Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.

Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.

Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.

Abstract: Disclosed is a method of simulating semiconductor circuitry in which trace data received from a first simulation of the semiconductor circuitry, is processed and the values of inputs to the semiconductor circuitry read from the trace data are output to a second simulation of semiconductor circuitry. There is also disclosed a method of determining whether first and second simulations of semiconductor circuitry are equivalent in which transitions in the values of registers simulated by the first and second simulations are analysed, and an error is declared if, following a register in either simulation making a transition to a value which is not equivalent to the corresponding register in the other simulation. The value of the register in the same simulation makes a further transition to a non-equivalent value before the value of the register in the other simulation makes a transition to an equivalent value.

Abstract: A communication system comprises an input-output processor IOP (11) coupled to a plurality of network devices (10) and a protocol processor PP (12), both processors being coupled to a common memory (15). Memory access control means (16) resolves competition between the processors for memory access. Normally, if one of the two processors is accessing the memory, the memory control unit (16) allows that access to be completed before allowing the other processor to access the memory. But if data loss in a network device is imminent, the IOP, is granted a higher priority memory access, the memory access controller aborts (interrupts) any memory access by the PP, allowing the IOP to access the memory immediately.