Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Abstract: A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Abstract: A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

Abstract: A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.

Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.

Abstract: A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.

Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.

Abstract: A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

Abstract: A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

Abstract: A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.

Abstract: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material.

Abstract: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.