Abstract: For an asynchronous memory control system, a system and method of interfacing the system with a synchronous memory device is provided. A first set of signals indicating an asynchronous memory operation from the control system and a first memory address associated with the asynchronous memory operation from the control system are received. Next, a second set of signals, a second memory address and at least one asynchronous clock pulse are generated, wherein the generated signals allowing processing of a comparable synchronous operation to the asynchronous operation by the synchronous memory device at the second memory address. The second set of signals and initiation, duration and frequency of the asynchronous clock pulse comply with requirements of the synchronous memory device to process the synchronous operation.