Patents by Inventor William S Burton

William S Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240066123
    Abstract: This provides pharmaceutical compositions that comprise (i) an anti-LAG-3 antibody or antigen binding fragment thereof or (ii) an anti-LAG-3 antibody or antigen binding fragment thereof and an anti-PD-1 antibody, anti-PD-L1 antibody, or antigen binding fragment thereof. Also provided are pharmaceutical compositions that comprise a buffering agent, stabilizing or bulking agent, and a surfactant. The disclosure also provides a vial, syringe, intravenous bag, or kit that comprises the compositions, and methods for using the compositions.
    Type: Application
    Filed: June 16, 2023
    Publication date: February 29, 2024
    Inventors: Lori S. BURTON, William Ying, Nils Lonberg, Sudhir Chakravarthi, Pedro Smith
  • Patent number: 8543967
    Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 24, 2013
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jason T. Gentry, Brian C. Miller, William S. Burton, M. Jason Welch, Richard A. Krzyzkowski
  • Publication number: 20130227508
    Abstract: A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: AVAGO TECHNOLOGIES FIBER IP (SINGAPORE) PTE. LTD.
    Inventors: Jason T. Gentry, Brian C. Miller, William S. Burton, M. Jason Welch, Richard A. Krzyzkowski
  • Patent number: 7405109
    Abstract: A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: July 29, 2008
    Assignee: Avago Technologies General IP Pte Ltd
    Inventor: William S Burton
  • Patent number: 6900533
    Abstract: An apparatus for routing electrical signals is a layered structure having a signal trace connected to a via and to a conductive stub trace on a first side. A reference layer is on a second side of the layered structure. Removing a portion of the conductive reference layer in an area of the stub strace increases the impedance of the stub trace without changing the impedance of the signal trace thereby improving an impedance match to another electrical element to which the apparatus is connected.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 31, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: William S Burton
  • Patent number: 6630628
    Abstract: A high-performance, integrated circuit interconnection laminate. Power/ground layers in laminates fabricated with open areas to permit out gassing of gases generated during high temperature lamination are located such that they do not lie under/over critical traces on signal layers. This placement of the open areas enables a reduction in cross-talk between signal layers lying on opposite sides of a power/ground layer and a reduction in signal delay.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: October 7, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Nurwati S Devnani, William S Burton, Sari K Christensen
  • Publication number: 20030148077
    Abstract: A high-performance, integrated circuit interconnection laminate. Power/ground layers in laminates fabricated with open areas to permit out gassing of gases generated during high temperature lamination are located such that they do not lie under/over critical traces on signal layers. This placement of the open areas enables a reduction in cross-talk between signal layers lying on opposite sides of a power/ground layer and a reduction in signal delay.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 7, 2003
    Inventors: Nurwati S. Devnani, William S. Burton, Sari K. Christensen
  • Publication number: 20030141107
    Abstract: An apparatus for routing electrical signals is a layered structure having at least one signal trace disposed on a first side of an electrically insulating layer with a via electrically connected to the trace. The via also has a conductive stub trace electrically connected thereto. A generally planar electrically conductive reference layer is on a second side of the electrically insulating layer and the stub trace on the first side defines an area on the second side where the electrically conductive layer is absent. Removing a portion of the conductive reference layer increases the impedance of the stub trace without changing the impedance of the signal trace thereby improving an impedance match to another electrical element to which the apparatus is connected.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventor: William S. Burton