Abstract: This disclosure is generally directed to communication systems, devices used in communication systems and associated methods which may implement parallel hypothesis search techniques. The disclosed parallel hypothesis search techniques may permit a hypothesis to be dismissed early (i.e., before hypotheses in other searchers have completed their evaluation). Early hypothesis dismissal permits a new hypothesis to be loaded into the searcher while other searchers advantageously continue to evaluate their hypotheses.

Abstract: A method and system for processing the results of searches for signals in a direct sequence spread spectrum communications system in an intelligent and efficient manner. A preferred embodiment comprises a search engine (for example, search engine 405) and a hardware result processor (for example, result processor 410) with a memory (for example, memory 415) as an interface. The search engine may perform multiple correlations of a pilot channel and then writes the correlation results exceeding a specified threshold to the memory. The result processor reads the correlation results from the memory and performs result filtering and builds a list of maximum value correlation results. The result processor and the search engine functions with independence from one another therefore, there is therefore, little wasted overhead where one has to wait for the other. The result filtering also makes it simpler to combine signal multipaths and simplifies pilot channel strength comparisons.

Abstract: In a system for transferring data between a host device and a target recording medium, a buffer interface control unit includes a host direct memory access (DMA) unit for transferring data from the host unit to a buffer memory. The host DMA unit accesses a first set of prescribed noncontinuous buffer memory storage locations to store the data transferred from the host unit in a predetermined buffer format that includes additional sets of prescribed storage locations interspersed with the first set of data storage locations for the storage of error code characters pertaining to the data. The host DMA unit also transfers error correction code characters pertaining to the data to one of the additional sets of prescribed storage locations. The buffer interface control unit further includes a target DMA unit for transferring data from the buffer memory to a write interface unit.