Patents by Inventor William S. Graupp
William S. Graupp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9940428Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.Type: GrantFiled: October 7, 2014Date of Patent: April 10, 2018Assignee: Mentor Graphics CorporationInventors: Fedor Pikus, Jimmy Jason Tomblin, William S. Graupp
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Publication number: 20160098512Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Fedor Pikus, Jimmy Jason Tomblin, William S. Graupp
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Patent number: 8832609Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: GrantFiled: July 22, 2013Date of Patent: September 9, 2014Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Patent number: 8813017Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.Type: GrantFiled: October 31, 2011Date of Patent: August 19, 2014Assignee: Mentor Graphics CorporationInventors: Jean-Marie Brunet, William S. Graupp
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Publication number: 20140201694Abstract: Techniques for “wrapping” functional geometric elements with fill geometric elements are provided. With some implementations, functional geometric elements, such as geometric elements representing metal contact and interconnect structures, are identified in layout design data. Next, fill regions requiring fill geometric elements are identified. If a portion of a functional geometric element faces a fill region, then that portion of the functional geometric element is “wrapped” with fill structures. Typically, the exposed portions of the functional geometric elements are wrapped before the remaining fill region is populated with fill geometric elements. By wrapping the exposed portions of the functional geometric elements, a designer can surround the functional geometric elements with a predictable pattern of fill geometric elements that can serve to protect the functional geometric elements from, for example, the capacitive effect of other fill geometric elements in the fill region.Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: Mentor Graphics CorporationInventor: William S. Graupp
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Publication number: 20130305195Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Patent number: 8504959Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: GrantFiled: November 7, 2011Date of Patent: August 6, 2013Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Publication number: 20120144350Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.Type: ApplicationFiled: October 31, 2011Publication date: June 7, 2012Applicant: Mentor Graphics CorporationInventors: Jean-Marie Brunet, William S. Graupp
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Publication number: 20120144351Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: ApplicationFiled: November 7, 2011Publication date: June 7, 2012Applicant: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Patent number: 8056022Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: GrantFiled: November 8, 2007Date of Patent: November 8, 2011Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Patent number: 8051393Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.Type: GrantFiled: July 14, 2009Date of Patent: November 1, 2011Assignee: Mentor Graphics CorporationInventors: Jean-Marie Brunet, William S. Graupp
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Patent number: 8015510Abstract: In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based on processing variation factors for the photolithographic process, which produces a generated contour object. A plurality of segments in the generated contour object may be determined based on processing variations. Segments are then broken up based on the processing variations that result. An adjusted width and adjusted length for each of the plurality of segments of the generated contour object are then determined. Resistances and capacitances may be extracted using the adjusted widths and adjusted lengths. Then, the output of the LVS tool may be sent to a SPICE simulation to verify the electrical behavior of the interconnect.Type: GrantFiled: February 16, 2007Date of Patent: September 6, 2011Assignee: Mentor Graphics CorporationInventors: Jean-Marie Brunet, William S. Graupp
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Publication number: 20090276749Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.Type: ApplicationFiled: July 14, 2009Publication date: November 5, 2009Applicant: Mentor Graphics CorporationInventors: Jean-Marie Brunet, William S. Graupp
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Patent number: 7577932Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.Type: GrantFiled: February 16, 2007Date of Patent: August 18, 2009Inventors: Jean-Marie Brunet, William S. Graupp
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Publication number: 20080141195Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.Type: ApplicationFiled: November 8, 2007Publication date: June 12, 2008Inventors: Juan Andres Torres Robles, William S. Graupp, Mark C. Simmons
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Patent number: 7253528Abstract: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.Type: GrantFiled: February 1, 2005Date of Patent: August 7, 2007Assignee: Avago Technologies General IP Pte. Ltd.Inventors: Walter John Dauksher, Wayne Patrick Richling, William S. Graupp
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Patent number: 7208843Abstract: A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.Type: GrantFiled: February 1, 2005Date of Patent: April 24, 2007Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Wayne Patrick Richling, Walter John Dauksher, William S. Graupp