Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.

Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.

Abstract: A system and method for isolating the timing domain of a central processing unit (CPU) from the timing domain of a memory bus is described. The CPU interfaces with memory and input/output through a dual clock domain interface (DCDI). The DCDI allows the CPU and memory to operate at frequency ratios of N:M, where N and M are positive integers, with N greater than or equal to M. The CPU operating clock speed is not constrained by the operating speed of the memory and input/output. The primary components of the DCDI are: 1) domain translation buffers, 2) clock control circuit, 3) output data queue and 4) receiver modifier circuits. A domain translation buffer takes data from one clock domain and translates it into another clock domain. The clock control circuit generates appropriate clocks according to the current frequency ratio of the system. An output data queue is required when the CPU generates data faster than the memory can accept.

Abstract: The invention comprises methods and apparatuses for interleaving a number of memory cards of different sizes. A restricted range modulo-N adder for identifying and selecting the correct interleave card is provided. Another aspect of the invention provides a computer system with flexible memory interleaving capability.

Abstract: A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master devices keep track of which parts of memory are busy by storing memory block identification numbers in local queues whenever memory is accessed. Block identification numbers are removed from local queues when the memory transaction is complete. Master devices arbitrate for access to the bus for memory transactions only if the target memory block identification number is not in the local queue.

Abstract: A method and circuitry for controlling priority of devices contending for access to a data communications link. Each device capable of contending for access contains a priority register which indicates the relative priority of every device capable of contending for access. After gaining access to the link, a device may optionally signal to all devices to update priority. When priority is updated, the device signaling priority update is moved to lowest priority. Inhibiting the signal to update priority permits a device to maintain priority. Systems using the method may be configured with a fair arbitration protocol (least recently accessed has highest priority), with fixed priority protocol, or with priority protocols that can be modified in real time.

Abstract: In a multiprocessor computer system, wasted bus bandwidth resulting from slow responding slaves is reduced by relinquishing the master that was busied by the slow responding slave, and then causing the slave to effectively arbitrate for bus control on the relinquished master's behalf when the slow responding slave is either available to service the master or has the requested data. In accordance with the disclosed embodiment, the slave effectively arbitrates for bus control on the relinquished master's behalf by placing a unique arbitration code associated with the relinquished master on the bus. The relinquished master detects the presence of its arbitration code and then again arbitrates for bus control so that it may communicate with the slow responding slave.

Abstract: A method and apparatus to improve computer bus access time. A bus is described which has sequential control states and fixed transaction times. Without the invention, arbitration may be delayed as the bus sequences through control states. With the invention, arbitration is immediate if the bus is idle. When any transaction is initiated, a counter is initialized to the number of control states in the standard transaction time. If the counter reaches zero, the bus is idle. If the bus is not idle, a sequence of bus control states is repeated. If the bus is idle, the bus is forced to remain in an arbitration state, thereby enabling any subsequent arbitration to take place immediately.

Abstract: A protocol for carrying out transactions in a multiple-processor computer system comprises: dividing the transaction cycle into four quadrature states, an arbitrate state, an I/O state, a slave address state and a virtual memory state. The protocol enables the processors to determine before arbitrating whether the memory device is busy, which reduces the number of "busied" transactions.

Abstract: A bus receiver includes a differential input amplifier circuits, a pair of source followers, and a sense amp having sense and latch modes. In a preferred embodiment of the invention, the bus receiver is implemented as a CMOS large scale integrated circuit comprising a plurality of FETs, and is capable of detecting .+-.0.2 volt transition of the data signal relative to a reference voltage for data signals having setup times as low as about 1 nanosecond.