Abstract: The current document is directed to methods and systems for secure provisioning, publication, distribution, and utilization of public-key certificates. These methods and systems employ domain name system (“DNS”) servers implementing the DNS security extensions (“DNSSEC servers”), a publisher component, and additional client-side and server-side functionalities. Public-key certificates provided by the DNSSEC servers engender a high degree of trust, as their integrity is protected and can be readily authenticated by the cryptographic-digital-signature based chains of trust provided by the DNSSEC. The systems to which the current document is directed employ DNSSEC servers, a publisher component, and additional client-side and server-side functionalities, and are referred to as “Public-key certificate Distribution and Management Systems” (“CDMSs”).

Abstract: Embodiments of the present invention include a variety of different integrated, multi-tiered methods and systems for preventing various types of attacks on computer systems, including denial-of-service attacks and SYN-flood attacks. Components of these integrated methods and systems include probabilistic packet droppers, packet-rate throttles, resource controls, automated firewalls, and efficient connection-state-information storage in memory resources and connection-state-information distribution in order to prevent draining of sufficient communications-related resources within a computer system to seriously degrade or disable electronics communications components within the computer system.

Abstract: The current application is directed to methods and systems for secure distribution of public-key certificates using the domain name system with security extensions (“DNSSEC”), a publisher component, and additional client-side functionality. These methods and systems, when combined with public/private-key-based cryptography used for encrypting digitally encoded information, provides a computationally efficient and well-understood method and system for secure communications and digitally-encoded-information verification without current difficulties and inefficiencies attendant with distributing and managing the public keys used for encrypting digitally encoded information.

Abstract: In various embodiments of the present invention, execution-state transitions occur in a first portion of a system, and a cumulative execution state for each process is maintained by a second portion of the system so that, when a second-portion routine is called, the second-portion routine can determine whether or not the current execution state is suitable for execution of the second-portion routine. In various embodiments, a callpoint log, allocated and maintained for each process, stores the cumulative execution state for the process. In one embodiment, the first portion is an operating system, and the second portion is a secure kernel, with the cumulative execution state used by the secure kernel to prevent unauthorized access by erroneously or maliciously invoked operating-system routines to secure kernel routines. In another embodiment, the cumulative execution state is used as a debugging tool by the second-portion routines to catch errors in the implementation of the first-portion routines.

Abstract: Methods and techniques for implementing a custom execution environment (CE2) and a related loader are provided. According to one embodiment, the CE2 includes code and data sections of an application and code and data sections of a set of system services. The set of system services has direct and full control of a set of hardware resources of a computer system containing one or more processors implementing a parallel protected architecture. According to one embodiment, the system services are designed for maximum simplicity, fastest possible speed, and elimination of security vulnerabilities.

Abstract: Operating system methods and techniques for supporting one or more custom execution environments (CE2s) are provided. According to one embodiment, a determination is made with respect to which system resources of a computer system, if any, are to remain under control of a resident operating system of the computer system and which of the system resources are to be placed under control of one or more CE2s. The system resources are then partitioned among the resident operating system and the one or more CE2s by associating one or more partitions of the system resources with the one or more CE2s. Such partitioning may be performed by the resident operating system by employing hardware-based isolation techniques provided by a processor of the computer system, performed by the resident operating system by employing a secure-platform interface, or configured by a system administrator via hardware partitioning capability provided by the computer system platform.

Abstract: A computer apparatus for creating a trusted environment comprising a trusted device arranged to acquire a first integrity metric to allow determination as to whether the computer apparatus is operating in a trusted manner; a processor arranged to allow execution of a first trust routine and associated first operating environment, and means for restricting the first operating environment access to resources available to the trust routine, wherein the trust routine being arranged to acquire the first integrity metric and a second integrity metric to allow determination as to whether the first operating environment is operating in a trusted manner.

Abstract: Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

Abstract: A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.

Abstract: An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Abstract: A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.

Abstract: A gamma correction circuit in which digitized video intensity values are divided into high and low intensity ranges. Every fourth high value is gamma corrected in a lookup table and written to a frame buffer. All of the low intensity values are written to the buffer without gamma correction. The data in the buffer is mapped by a second lookup table before being converted to an analog signal. The second table maps the low intensity values to gamma corrected values and does not change the value of the high intensity values. When data is read from the frame buffer for further processing before display on a CRT, the lower intensity values need not be inverse gamma corrected. The high intensity values are inverse gamma corrected via a lookup table before such further processing.

Abstract: A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

Abstract: Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

Abstract: Apparatus is provided which interrupts arithmetic and logical operations defined by a major opcode instruction if the resultant overflows its defined length. One major opcode defines the arithmetic and logical operations between two operands in registers and the result, zero, one, the generated condition or first operand is stored in a register.

Abstract: One program in one address space is permitted to obtain access to data in another address space or to call a program in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space. A program changeable space selection control bit controls use of two different sets of address translation tables associated with two different address spaces. Without invoking a supervisor, a particular program in an assigned address space can call a program in another address space or obtain addressability to data in another address space having an associated set of address translation tables.