Abstract: A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.

Abstract: A gamma correction circuit in which digitized video intensity values are divided into high and low intensity ranges. Every fourth high value is gamma corrected in a lookup table and written to a frame buffer. All of the low intensity values are written to the buffer without gamma correction. The data in the buffer is mapped by a second lookup table before being converted to an analog signal. The second table maps the low intensity values to gamma corrected values and does not change the value of the high intensity values. When data is read from the frame buffer for further processing before display on a CRT, the lower intensity values need not be inverse gamma corrected. The high intensity values are inverse gamma corrected via a lookup table before such further processing.

Abstract: A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

Abstract: Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

Abstract: Apparatus is provided which interrupts arithmetic and logical operations defined by a major opcode instruction if the resultant overflows its defined length. One major opcode defines the arithmetic and logical operations between two operands in registers and the result, zero, one, the generated condition or first operand is stored in a register.

Abstract: One program in one address space is permitted to obtain access to data in another address space or to call a program in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space. A program changeable space selection control bit controls use of two different sets of address translation tables associated with two different address spaces. Without invoking a supervisor, a particular program in an assigned address space can call a program in another address space or obtain addressability to data in another address space having an associated set of address translation tables.

Abstract: Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be specified by a program if authorized in accordance with the entry of an authority table associated with the second address space, the entry being designated by an authorization index associated with the program.

Abstract: Permits one program in one address space to obtain access to data in another address space or to call a program in another address space without invoking a supervisor, with authorization to use a storage protect key other than that specifically assigned to the program by a supervisor when in a new semi-privileged state. Programs executing in a particular address space have supervisor assigned storage protect key masks permitting the program, when authorized, to utilize a storage protect key other than the one specifically assigned by the supervisor. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space, and two different storage protect keys can be utilized.