Abstract: An information processing system includes a first data processing device 10 and a second data processing device 12 each of which is capable of independent instruction execution during instruction cycles having a period which is a multiple of a periodic unit clock signal period. The devices are disclosed to be an arithmetic unit and a central processor which are coupled together by an interface 14. Each of the data processing devices include a clock generation device 180 having an input coupled to the unit clock signal for generating an associated instruction cycle clock signal which has a period which is a multiple of the unit clock signal period. The clock generation device is further operable for suspending the generation of the instruction cycle clock signal and for beginning a next instruction cycle clock signal in synchronism with a transition of the unit clock signal.

Abstract: An information processing system includes a first data processing device 10 and a second data processing device 12 each of which is capable if independent instruction execution during instruction cycles having a period which is a multiple of a periodic unit clock signal period. The devices are disclosed to be an arithmetic unit and a central processor which are coupled together by an interface 14. Each of the data processing devices include a clock generation device 180 having an input coupled to the unit clock signal for generating an associated instruction cycle clock signal which has a period which is a multiple of the unit clock signal period. The clock generation device is further operable for suspending the generation of the instruction cycle clock signal and for beginning a next instruction cycle clock signal in synchronism with a transition of the unit clock signal.