Abstract: Systems and methods for executing queries on a bitmap index are disclosed. The system may receive a first data stream from a database and generate a bitmap index based on the first data stream. The system may receive an input selection of one or more data conditions from a user device and generate a Boolean expression based on the input selection. The system may query the bitmap index using the Boolean expression and generate a bitmap vector. The system may output a first data subset represented by the generated bitmap vector to a graphical user interface. The bitmap index may include probabilistic entries, and the system may validate the probabilistic entries by receiving a second data stream, identifying one or more entries correlated to the probabilistic entries, determining a divergence between the identified entries and the probabilistic entries, and updating parameters of a classifier model associated with the probabilistic entries.

Abstract: A system can include an emitter structure connected to a reservoir containing a working material, wherein the working material is in electrical communication with a first electrode, an electrode opposing the emitter structure across a gap; and optionally a frame holding the emitter structure and the electrode.

Abstract: Pressure sensors having ring-tensioned membranes are disclosed. A tensioning ring is bonded to a membrane in a manner that results in the tensioning ring applying a tensile force to the membrane, flattening the membrane and reducing or eliminating defects that may have occurred during production. The membrane is bonded to the sensor housing at a point outside the tensioning ring, preventing the process of bonding the membrane to the housing from introducing defects into the tensioned portion of the membrane. A dielectric may be introduced into the gap between the membrane and the counter electrode in a capacitive pressure sensor, resulting in an improved dynamic range.

Abstract: An example air barrier system for a data center within a building is disclosed. The example air barrier system includes a pliable barrier material to partition an area above a top of row of computer cabinets in the data center and below an overhead surface of the building. The pliable barrier material is to reduce mixing of air between first and second aisles on opposites sides of the row of computer cabinets. The example air barrier system also includes a frame to support the pliable barrier material in position when in the area above the top of the row of computer cabinets. The frame is to be supported by the row of computer cabinets without support from the overhead surface.

Abstract: Apparatus for tensioning pliable airducts while supporting internal HVAC components are disclosed. An airduct system includes an airduct having a tubular wall of a pliable material. The airduct is elongate in a longitudinal direction. The airduct system further includes a frame including a hoop disposable inside the airduct to support the tubular wall in a radial direction that is perpendicular to the longitudinal direction. The hoop is less flexible than the pliable material. The airduct system also includes a sensor to be attached to the frame to be in fluid communication with a current of air within the airduct. The sensor is to provide a feedback signal that varies in response to a changing condition of the current of air.

Abstract: A computer-implemented method for detecting anomalies in computing systems includes measuring activity metrics associated with accessing resources of the system by several users. Further, condensed diagnostic data is generated by grouping the users into buckets based on bucket and user attributes, and aggregating the activity metrics across all users in each bucket. Bucket contents are recorded during system's use, during which, analytic embedded data is generated for anomaly detection. The generating includes, for each bucket, capturing the activity metrics for an exceptional user in each bucket without aggregation at a next time interval.

Abstract: A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: A method implemented by a system for security comprising an unmanned aerial vehicle (UAV) and an analytics device configured to communicate with a remote monitoring system and the UAV is provided. Media data from the UAV is received at an analytics device, where the media data includes surveillance information corresponding to a premises under surveillance. Security attributes associated with the premises are detected based at least in part on a first level of machine learning (ML) analysis performed on the media data. The media data are transmitted by the analytics device to the remote monitoring system for a second level of ML analysis based at least in part on the security attribute, where the first level of ML analysis is less computationally expensive compared to the second level of ML analysis, and the second level of ML analysis is performed at the remote monitoring system on the media data.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Abstract: Systems and methods are provided for blocking charges from a merchant to a payment account of a user. An exemplary system may include one or more memory devices storing instructions and one or more processors configured to execute the instructions to perform various operations. The operations may include receiving, from the user, a dispute request to dispute a charge to the payment account applied by the merchant. In response to the dispute request, the operations may include determining whether to block subsequent charges applied by the merchant to the payment account, based on a history of charging activities of the merchant. Responsive to a determination to block subsequent charges, the operations may include adding the merchant to a block-charge list associated with the payment account.

Abstract: Systems and methods are provided for blocking charges from a merchant to a payment account of a user. An exemplary system may include one or more memory devices storing instructions and one or more processors configured to execute the instructions to perform various operations. The operations may include receiving, from the user, a dispute request to dispute a charge to the payment account applied by the merchant. In response to the dispute request, the operations may include determining whether to block subsequent charges applied by the merchant to the payment account, based on a history of charging activities of the merchant. Responsive to a determination to block subsequent charges, the operations may include adding the merchant to a block-charge list associated with the payment account.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.

Abstract: Embodiments of the invention are directed to intelligently and dynamically controlling both changes made within EUC applications and the control rules associated with such changes. A similarity index is calculated/assigned for each data entry field (i.e., cell/intersection) and the controls implemented when a changes to data in the entry fields occurs is based on the similarity index. In other embodiments, a change to data entry fields dynamically prompts analysis of the change based on historical approval and/or denial patterns specific to the EUC application, the data entry field(s) and/or the user of the application. In response to the analysis the control rules may be dynamically updated, and applied to the current change. In other embodiments, inputs, such as reviewer's comments, are the basis for determining a need to update existing controls or add new controls associated with data entry field(s) and the conditions associated therewith are determined and applied.

Abstract: A Venturi pump chlorine dioxide generation device with one or more special ninety-degree bends with half-spherical mixing stations including: at least one ninety-degree bend with two half-spherical mixing stations between the sodium hypochlorite introduction point and the acid source introduction point, at least two ninety-degree bends with two half-spherical mixing stations between the acid source point and the sodium chlorite introduction point, and at least two ninety-degree bends with two half-spherical mixing stations between the sodium chlorite introduction point and the vacuum chamber of the Venturi pump. Each ninety-degree bend with two half-spherical mixing stations is an elbow section of cylindrical conduit or pipe wherein the two outer segments of the ninety-degree bend each have a spherical shaped expansion area to create a half-spherical concave section inside the conduit or pipe.

Abstract: An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Abstract: An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.