Abstract: An interposer is described. The interposer includes a top layer including an array of passive devices integrated into the top layer. A number of the passive devices may be connected to a pad by a trace disposed above the top layer. The number of the passive devices may be selected to achieve a desired property for the array, such as a desired resistance, inductance, or capacitance. The interposer may thus provide an ability to rapidly tune a die coupled to the pad of the interposer based on the arrangement of the trace.

Abstract: A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alternative stress path that substantially bypasses the transistor.

Abstract: A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alterative stress path that substantially bypasses the transistor.

Abstract: A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.

Abstract: A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.