Abstract: One aspect of systems and methods for segment size estimation includes identifying a segment of users for a first time period based on time series data, wherein the time series data includes a series of interactions between users and a content channel and wherein the segment includes a portion of the users interacting with the content channel during the first time period; computing a segment return value for a second time period based on the time series data by computing a first subset and a second subset of the segment, wherein the first subset includes users that interact with the content channel greater than a threshold number of times during a range of the time series data and the second subset comprises a complement of the first subset with respect to the segment; and providing customized content to a user in the segment based on the segment return value.

Abstract: The calibration system of the farming machine receives images from each camera of the camera array. The images comprise visual information representing a view of a portion of an area surrounding the farming machine. To calibrate a pair of cameras including a first camera and second camera, the calibration system determines a relative pose between the pair of cameras by extracting relative position and orientation characteristics from visual information in both an image received from the first camera and an image received from the second camera. The calibration system identifies a calibration error for the pair of cameras based on a comparison of the relative pose with an expected pose between the first pair of cameras. The calibration system transmits a notification to an operator of the farming machine that describes the calibration error and instructions for remedying the calibration error.

Abstract: A system may include one or both of a light emitter and a light receiver. The system may include an optical filter adjacent one or both of the light emitter or the light receiver. The optical filter includes a wavelength selective scattering layer. The wavelength selective scattering layer may have a near-infrared scattering ratio of less than about 0.9. The filter may have a visible reflective haze ratio of greater than about 0.5. A method may include disposing the wavelength selective scattering layer adjacent one or both of the light emitter and the light receiver. An article may include the optical filter. The wavelength selective scattering layer may have an average near-infrared scattering of less than 60%, an average visible scattering of greater than 10%, and a difference between the % total visible reflectance and the % diffuse visible reflectance of less than 20.

Abstract: The disclosure describes techniques for interacting with visitors at a visitor interaction system. A method includes obtaining video data captured by the visitor interaction system, identifying an approach of a person, and analyzing the video data to determine an identity of the person. The method includes automatically and without user intervention determining that the person belongs to a visitor groups of a plurality of visitor groups. Each of the visitor groups corresponds to a response model that includes a plurality of response actions. At least one of the response actions includes an autonomous response action. The method includes identifying a response model corresponding to the visitor groups and initiating an autonomous response action associated with the response model. Initiating the autonomous response action including presenting a message to the person, monitoring a response to the message, and sending a report message to the user via a client device.

Abstract: A composition comprising acetylene fluid at least partially solubilized in an improved solvent is described. The improved solvents exhibit non-toxicity and are further characterized by low vapor pressures to minimize solvent carryover during delivery of the acetylene fluid, while retaining suitable acetylene solubilizing capacity.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

Abstract: A hashing system (e.g., including a message expander) receives word data associated with a message. The hashing system identifies a plurality of message expansion computations that are configured to use the word data to generate a hash for the message. The hashing system pre-computes at least one message expansion computation of the plurality of message expansion computations using the word data to generate at least one constant. The hashing system executes a modified plurality of message expansion computations to generate the hash of the message. Executing the modified plurality of message expansion computations includes replacing the at least one message expansion computation of the plurality of message expansion computations with the at least one constant.

Abstract: A hashing system includes data storage circuit elements that store words to be used for hashing a message. Each data storage circuit element stores a word without moving the word to any other data storage circuit element during hashing. The hashing system includes combinational logic circuit element(s) that select specified data storage circuit elements according to a specified order that simulates shifting of at least a subset of the words among the data storage circuit elements, for instance based on an order in which the words were stored and/or based a clock. The hashing system includes computational operator(s) that generate additional word(s) based on the selected specified words. The hashing system stores the additional word(s) into available data storage circuit element(s), in some cases overwriting prior word(s) that were stored in the available data storage circuit element(s). The hashing system can include a message expander (ME) and/or message compressor (MC).

Abstract: The invention determines a method that compares the performance of different gaming devices. The method makes use of simultaneously played videos that consist of identical, in terms of the video game played and the starting point of the video, gameplay footage to allow the user to compare the performances of the selected devices through visual inspection. A single button, when clicked, will begin the simultaneous play of all videos. In addition, the number of videos that will be simultaneously played is equal to the number of devices chosen by the user, with one video corresponding to each chosen device. Performance data will be displayed in frames per second (FPS), graphics processing unit usage (GPU) and central processing unit usage (CPU).

Abstract: A pump pulling apparatus that is adapted for attachment to a vertical LFG well for the purpose of moving a pump such as a dewatering pump up and down the well. The apparatus is an upright vertical column on which a reversible winch is mounted. The column may be secured to the wellhead and a cable attaches to the down-well pump and the winch is operable to lower the pump into the well and to raise the pump out of the well.

Abstract: A multi-directional drill-type device that can be shuttled vertically through well casings of various diameters to add new perforations at the desired spacing and positions along the casings to optimize well performance is disclosed. The apparatus is especially suited to add perforations to well casings of existing vertical LFG extraction wells. The apparatus includes a motor in a housing that may be purged with inert gas and with an output shaft that rotates around a first axis. The motor output shaft drives plural drill assembly modules that have drill bits that rotate around an axis normal to the first axis and which reciprocate into and out of the apparatus.

Abstract: A multi-directional drill-type device that can be shuttled vertically through well casings of various diameters to add new perforations at the desired spacing and positions along the casings to optimize well performance is disclosed. The apparatus is especially suited to add perforations to well casings of existing vertical LFG extraction wells. The apparatus includes a motor in a housing that may be purged with inert gas and with an output shaft that rotates around a first axis. The motor output shaft drives plural drill assembly modules that have drill bits that rotate around an axis normal to the first axis and which reciprocate into and out of the apparatus.

Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.

Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.

Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Abstract: Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.