Abstract: A system and a method for a multiple state, multiple case counter circuit are disclosed. The counter circuit has a n position register, n being any integer. Each of the n position counts from 1 to 9. In one embodiment of the present invention, the register takes 9 states (state 1 to state 9). In another embodiment of the present invention, the register has 10 states (state 0 to state 9). Furthermore, the register takes n cases in each state. The counter circuit uses one of the n positions of the register to indicate a state of the register and uses the remaining (n-1) positions to count the NEs. The counter circuit counts 9.times.n.times.(1.sup.n-1 -1) NEs when the register has 9 states. Likewise, the counter circuit counts 10.times.n.times.(10.sup.n-1 -1) NEs when the register has 10 states.