Patents by Inventor William Starks
William Starks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250051092Abstract: This disclosure provides methods, devices, and systems that may include a container housing having at least one opening, as well as a camera configured to capture a visual input relating to a deposited object placed into the at least one opening. A light source may be configured to illuminate the deposited object, and a sorting plate configured to divert the deposited object into one of a plurality of containers. A motor may be configured to move the sorting plate, and a processor system configured to: receive the visual input from the camera, classify the deposited object based on the visual input, and cause the motor to move the sorting place to divert the deposited object to the one of the plurality of containers based on the classification.Type: ApplicationFiled: August 11, 2023Publication date: February 13, 2025Inventors: John Jennings Calhoun Starke, John William Starke
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Patent number: 10649853Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 21, 2018Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10613940Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: November 7, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Guy Lynn Gutherie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10346255Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 22, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10339009Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 22, 2018Date of Patent: July 2, 2019Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10152385Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: July 3, 2014Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10133641Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: November 7, 2017Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10108498Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: February 19, 2016Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Publication number: 20180250287Abstract: An abuse deterrent opioid formulation for rectal use. The formulation contains a therapeutically effective amount of the opioid buprenorphine or salts and homologs thereof; and either a gel with a diminishing agent or a suppository base with a diminishing agent into which the opioid buprenorphine is mixed.Type: ApplicationFiled: March 6, 2018Publication date: September 6, 2018Inventors: A. Mike Schwarz, Daniel R. Kimbell, Charles William Stark
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Publication number: 20180101850Abstract: A computing device supports a Web Authentication (WebAuthN) application program interface (API) that is configured to exposes functionalities that may substitute for those utilized in the EMV (Europay, Mastercard, and Visa) standard for transactions using smart payment instruments like debit and credit cards that include embedded computer chips. The functionality of the WebAuthN-compliant computing device is analogous to a physical card in the conventional chip and PIN (personal identification number) where the chip serves as proof of payment device and the PIN as proof of payment account holder.Type: ApplicationFiled: August 11, 2017Publication date: April 12, 2018Inventors: Matthias Bernard Pisut, IV, Jonathan Lee Cutler, Michael William Stark
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Patent number: 9886350Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: February 19, 2016Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 9880905Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: July 2, 2014Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 9383049Abstract: A gripping device may be used to grip an inserted member. The gripping device has a body. The body defines a passage extending therethrough between opposite longitudinal ends. The body has an outer surface and an inner surface. The body includes at least three gripping elements spaced apart around the inner surface. Each of the gripping elements has a gripping surface for gripping an outer surface of the inserted member. Each of the gripping elements is movable upon application of a radial inward force to the outer surface of the body to reduce the spacing between adjacent gripping elements.Type: GrantFiled: May 2, 2011Date of Patent: July 5, 2016Assignee: Cambridge Brass, Inc.Inventors: Valer Stratulat, Donald William Stark
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Publication number: 20120280486Abstract: A gripping device may be used to grip an inserted member. The gripping device has a body. The body defines a passage extending therethrough between opposite longitudinal ends. The body has an outer surface and an inner surface. The body includes at least three gripping elements spaced apart around the inner surface. Each of the gripping elements has a gripping surface for gripping an outer surface of the inserted member. Each of the gripping elements is movable upon application of a radial inward force to the outer surface of the body to reduce the spacing between adjacent gripping elements.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Inventors: Valer Stratulat, Donald William Stark
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Patent number: 8255322Abstract: Bank float is assigned using a dual source bank float system by first determining which of a plurality of checks will be processed via a paper route and which will be processed via an image route. For the checks that will be processed via the paper route, a set of rules will be determined. For the checks that will be processed via the image route, a different set of rules will be determined. A bank float is applied to the paper checks using the paper set of rules and bank float is assigned to the image checks using the image set of rules.Type: GrantFiled: December 29, 2008Date of Patent: August 28, 2012Assignee: Bank of America CorporationInventors: Kenneth Lee Jaramillo, Douglas P Elliott, James Alan Kramer, Jr., Melvin Gregory Nixon, James William Stark, III
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Patent number: 8122913Abstract: A hose or cable protector has a pair of articulating guides, each with rollers for creating an arcuate hose path around the sharp corner of a tunnel mouth which would otherwise cause abrasion to the hose. A stop imposes a guide to guide angle of eighty (80) degrees but the usual angle is greater and up to one hundred and twenty (120) degrees. Arches span the guides and retain the protector on the hose or cable. In a variant, the arches are spring loaded and adjustable to retain or release the hose. A control line positions the protector at the selected site.Type: GrantFiled: January 12, 2010Date of Patent: February 28, 2012Inventor: Gordon William Stark
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Publication number: 20100175773Abstract: A hose or cable protector has a pair of articulating guides, each with rollers for creating an arcuate hose path around the sharp corner of a tunnel mouth which would otherwise cause abrasion to the hose. A stop imposes a guide to guide angle of eighty (80) degrees but the usual angle is greater and up to one hundred and twenty (120) degrees. Arches span the guides and retain the protector on the hose or cable. In a variant, the arches are spring loaded and adjustable to retain or release the hose. A control line positions the protector at the selected site.Type: ApplicationFiled: January 12, 2010Publication date: July 15, 2010Inventor: Gordon William Stark
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Publication number: 20100169201Abstract: Bank float is assigned using a dual source bank float system by first determining which of a plurality of checks will be processed via a paper route and which will be processed via an image route. For the checks that will be processed via the paper route, a set of rules will be determined. For the checks that will be processed via the image route, a different set of rules will be determined. A bank float is applied to the paper checks using the paper set of rules and bank float is assigned to the image checks using the image set of rules.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: BANK OF AMERICA CORPORATIONInventors: Kenneth Lee Jaramillo, Douglas P. Elliott, James Alan Kramer, JR., Melvin Gregory Nixon, James William Stark, III
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Publication number: 20080098177Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Inventors: Guy Guthrie, William Starke, Derek Williams, Philip Williams
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Publication number: 20080091885Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.Type: ApplicationFiled: December 13, 2007Publication date: April 17, 2008Inventors: Guy Guthrie, William Starke, Derek Williams, Philip Williams