Abstract: A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a second integrated device coupled to the first metallization portion; a first encapsulation layer coupled to the first metallization portion; a first passive device located in the first encapsulation layer; a first bridge located in the first encapsulation layer; a second metallization portion; a second integrated device coupled to the second metallization portion; a second integrated device coupled to the second metallization portion; a second encapsulation layer coupled to the second metallization portion; a second passive device located in the second encapsulation layer; and a second bridge located in the second encapsulation layer. The package further comprises a third metallization portion and a third encapsulation layer.

Abstract: A package comprising a first metallization portion; a second metallization portion; a first passive device coupled to the second metallization portion; a first encapsulation layer located between the first metallization portion and the second metallization portion; a first integrated device coupled to the first metallization portion; a second integrated device coupled to the first metallization portion; a dummy silicon structure located laterally between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the first metallization portion, wherein the second encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure.

Abstract: A package comprising a metallization portion; an integrated device comprising a plurality of pillar interconnects, wherein the integrated device is coupled to the metallization portion through the plurality of pillar interconnects; and an encapsulation layer at least partially encapsulating the integrated device, wherein the encapsulation layer is coupled to the metallization portion.

Abstract: A device comprising a substrate, a package coupled to the substrate, and a lid frame coupled to the substrate. The package comprises a first integrated device and an encapsulation layer that at least partially encapsulates the first integrated device. The lid frame is further coupled to the first integrated device through a thermal interface material. The lid frame is further coupled to the encapsulation layer through an adhesive.

Abstract: A package comprising a package interposer and a first integrated device coupled to the package interposer. The package interposer comprises a first metallization portion; a second metallization portion; a passive device located between the first metallization portion and the second metallization portion. The passive device comprises a plurality of bump interconnects. The plurality of bump interconnects comprise a first plurality of bump interconnects, where each bump interconnect from the first plurality of bump interconnects comprises a first minimum width; and a second plurality of bump interconnects, where each bump interconnect from the second plurality of bump interconnects comprises a second minimum width that is greater than the first minimum width.

Abstract: A device comprising a substrate; a package coupled to the substrate, a second integrated device coupled to the substrate; and a lid frame coupled to the substrate, wherein the lid frame comprises an opening located vertically over the second integrated device. The package comprises a package interposer comprising a first metallization portion; a second metallization portion; a passive device located between the first metallization portion and the second metallization portion; and a first integrated device coupled to the package interposer.

Abstract: A package comprising a first integrated device; a package interposer coupled to the first integrated device; and a passive device located at least partially in the package interposer. The passive device comprises a passive device substrate; a plurality of trench capacitors located at least partially in the passive device substrate; a plurality of through substrate vias extending through the passive device substrate; and a protection layer that is part of a first surface of the passive device, wherein the protection layer comprises an encapsulation layer or a polymer dielectric layer.

Abstract: A package comprising a first integrated device; a second integrated device; and a package interposer coupled to the first integrated device and the second integrated device. The package interposer comprises a first metallization portion; a second metallization portion; a first encapsulation layer coupled to the first metallization portion and the second metallization portion; and a passive device located at least partially in the first encapsulation layer. The first encapsulation layer and the passive device are located between the first metallization portion and the second metallization portion.

Abstract: A carriage unit for binder jetting additive manufacturing of components. A carriage body is movably mounted to a carriage frame within a printer unit and configured to traverse relative to a work surface. Two compaction rollers are mounted to the carriage body. Each is configured to move between a retracted position disengaged from build material powder to a deployed condition to recoat build material powder over a work surface. A powder dispensing unit is mounted to the carriage body and configured to dispense a metered amount of the build material powder as the carriage body traverses over the work surface. A print head mounted to the carriage body is configured to deposit a predetermined pattern of binder as the carriage unit traverses relative to the work surface.

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability.

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects located at least partially in the at least one dielectric layer. The frame may be an embedded frame.

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Abstract: An AI-based system and method for feed monitoring in a land-based fish farm, where the fish farm has a tank containing fish and an effluent pipe that is coupled to the tank where uneaten feed pellets and non-pellet objects flow through the effluent pipe to an exit port. A feed camera is mounted to an effluent pipe for capturing a video feed having images of objects that traverse a field of view of the feed camera when each image is acquired. A special-purpose computer executes a pellet-tracking algorithm that employs a region of interest (ROI) proposal module, an ROI classification module, an ROI tracking module, and a trajectory classification module for at least counting uneaten feed pellets. The computer generates in real time a pellet count based on the pellet trajectories.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability.

Abstract: Embodiments for an AI-based system and method for feed monitoring in a land-based fish farm are described where the system may include: a feed camera mounted to an effluent pipe for capturing a video feed having images of objects that traverse a field of view of the feed camera when each image is acquired; and a special-purpose computer that executes a pellet-tracking algorithm that employs a region of interest (ROI) proposal module, an ROI classification module, an ROI tracking module, and a trajectory classification module for at least counting uneaten feed pellets. In at least one embodiment, an object enhancer may be mounted to the effluent pipe opposite to and in the field of view of the feed camera to provide a background so that the objects in the acquired images have a definable perimeter.

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.