Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A truss section, comprising at least three parallel elongated structural members, said members defining a first cross-section, said members having two ends, said truss sections including means for end-wise coupling a plurality of said truss sections to assemble a longer load-bearing span, the improvement comprising an additional elongated structural member parallel to and structurally interconnected with at least two of said elongated structural members, said additional elongated structural member located substantially within said first cross-section, so as to define between said at least two and said additional elongated structural members, an elongated volume having a generally triangular cross-section.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.

Abstract: Error detection mechanisms for signal interfaces, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms are provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or are coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators and mechanisms for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface, a group of interfaces or may operate with a master device that tests a plurality of interfaces by sending test signals for storage by and retrieval from one or more slave memory devices. The error detection mechanisms test memory circuits designed to communicate according to multi-PAM signals over printed circuit boards.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols in constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

Abstract: A truss section comprising at least three parallel elongated structural members, said members defining a first cross-section, said members having two ends, said truss sections including means for end-wise coupling a plurality of said truss sections to assemble a longer load-bearing span, the improvement comprising an additional elongated structural member parallel to and structurally interconnected with at least two of said elongated structural members, said additional elongated structural member located substantially within said first cross-section, so as to define between said at least two and said additional elongated structural members, an elongated volume having a generally triangular cross-section.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments of the present invention. In a first embodiment of the present invention, logic is provided in a CDR unit of a serial receiving circuit by disengaging or freezing the CDR loop during a waveform capture mode. In a second embodiment of the present invention, an additional clock phase adjuster and sampling stage is used to generate offset clock signals independent of CDR tracking clocks. In a third embodiment of the present invention, edge clocks alone are used for CDR tracking of half rate serial data while data clocks are used for capturing a waveform. In a fourth embodiment of the present invention, a predetermined pattern having a single transition is used for CDR tracking.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.