Abstract: A display control device is connected to and controls a display device. The display control device comprises a frame buffer store, and a control component. The display control device is arranged to receive (S1) compressed display data, store (S2) the received compressed display data in the frame buffer store, and for each frame refresh of the display device access (S3) stored compressed display data, decompress (S4) the accessed display data, and output S5 the decompressed display data.

Abstract: A method of generating an image comprises receiving a signal over a USB interface comprising encoded display data for one or more groups of pixels within an image, the encoded display data comprising display data for less than the whole of the image, and position data for the or each group of pixels. The encoded display data is decoded to generate pixel data for each group of pixels. A frame buffer, which may be part of the display, is then updated with the generated pixel data according to the position data ready for output to the display device.

Abstract: A method of generating an image comprises receiving a signal over a USB interface comprising encoded display data for one or more rectangular group of pixel tiles within an image and position data for the or each group of pixel tiles. The coefficients are obtained from the encoded display data, maybe by converting variable bit length fields into AC coefficients and an inverse Haar transform performed on them to generate pixel data for each rectangular group of pixel tiles. A frame buffer, which may be part of the display, is then updated with the generated pixel data ready for output to the display device. Copy protection may also be incorporated using AES negotiated over HDPC.

Abstract: We describe an ultra wideband (UWB) orthogonal frequency division multiplexed (OFDM) modified dual carrier modulation (MDCM) decoder comprising: first and second inputs to input first and second signals for first and second OFDM carriers; third and fourth inputs for respective third and fourth signals comprising channel quality estimates for the OFDM carriers; a set of integer arithmetic units coupled to said first, second, third and fourth inputs to form a set of intermediate terms; a first set of adders to form first and second sets of combinations of said intermediate terms, one for each MDCM coded bit value; a compare-select stage to select a first and second minimum valued said combination of said intermediate terms from said first and second set; and a subtracter to determine a log likelihood ratio (LLR) value for said bit from said first and second minimum valued combinations.

Abstract: A display control device is connected to and controls a display device. The display control device comprises a frame buffer store, and a control component. The display control device is arranged to receive (S1) compressed display data, store (S2) the received compressed display data in the frame buffer store, and for each frame refresh of the display device access (S3) stored compressed display data, decompress (S4) the accessed display data, and output S5 the decompressed display data.

Abstract: A method of generating an image comprises receiving a signal over a USB interface comprising encoded display data for one or more rectangular group of pixel tiles within an image and position data for the or each group of pixel tiles. The coefficients are obtained from the encoded display data, maybe by converting variable bit length fields into AC coefficients and an inverse Haar transform performed on them to generate pixel data for each rectangular group of pixel tiles. A frame buffer, which may be part of the display, is then updated with the generated pixel data ready for output to the display device. Copy protection may also be incorporated using AES negotiated over HDPC.

Abstract: We describe an ultra wideband (UWB) orthogonal frequency division multiplexed (OFDM) modified dual carrier modulation (MDCM) decoder comprising: first and second inputs to input first and second signals for first and second OFDM carriers; third and fourth inputs for respective third and fourth signals comprising channel quality estimates for the OFDM carriers; a set of integer arithmetic units coupled to said first, second, third and fourth inputs to form a set of intermediate terms; a first set of adders to form first and second sets of combinations of said intermediate terms, one for each MDCM coded bit value; a compare-select stage to select a first and second minimum valued said combination of said intermediate terms from said first and second set; and a subtracter to determine a log likelihood ratio (LLR) value for said bit from said first and second minimum valued combinations.

Abstract: A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a quality of service engine (QoS Engine) which accelerates the processing of packets in a packet switching networks, such as an ATM network, by assisting the accurate pacing of many ATM virtual circuits. The QoS Engine allows the concurrent support of a wide variety of port speeds, traffic classes using different priorities and traffic parameters. quality of service engine (QoS Engine) works in conjunction with a network processor (NP) to allow it to maintain software flexibility, and for it to achieve accurate pacing.

Abstract: A distributed reservation protocol for medium access control in a multiband OFDM ultrawideband communications network having a band group comprising a plurality of transmission bands, a device in said network having a mode in which it uses a selected one of said bands to communicate, and a band hopping mode, and wherein the protocol comprises allowing a device in a group of devices to make a combined time-frequency reservation, said time-frequency reservation comprising a reservation of a combination of a subset of said bands in a said band group and one or more data communications timeslots in which the device is allowed to use said reserved band for data communications such that multiple said devices in said group are able simultaneously to use one or more of the same or overlapping said reserved timeslots in different reserved frequency bands of said band group.

Abstract: The invention relates to communications protocols for very high-speed data transmission, in particular burst mode packet data communications for ultra wideband (UWB) communications systems. We describe a method of sending a burst of data packets from a first OFDM transceiver to a second OFDM transceiver, said transceivers having a set of OFDM synchronisation symbols for synchronising communications between the transceivers, the method comprising: sending said data packets from said first to said second transceiver, and between sending at least some of said data packets of said bursts receiving acknowledgement data from said second transceiver at said first transceiver; and wherein said acknowledgement data is encoded using said OFDM synchronisation symbols.

Abstract: This invention is generally concerned with data communications systems, more particularly systems for communicating between two software processes through an intervening firewall.

Abstract: A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a quality of service engine (QoS Engine) which accelerates the processing of packets in a packet switching networks, such as an ATM network, by assisting the accurate pacing of many ATM virtual circuits. The QoS Engine allows the concurrent support of a wide variety of port speeds, traffic classes using different priorities and traffic parameters. quality of service engine (QoS Engine) works in conjunction with a network processor (NP) to allow it to maintain software flexibility, and for it to achieve accurate pacing.

Abstract: A method and processor for FIR filtering a series of real input values with a series of filter coefficients where each of the input values is loaded from memory into the processor, and the processor employs each loaded input value in computing more than one filter output value at a time, whereby the amount of data which needs to be transferred between memory and the processor is substantially reduced. The filter output values are preferably real data values, although the invention could be adapted to operate on complex number pairs. More than one input value can be loaded from memory in each clock cycle. Computations can be made by a multiply-and-accumulate unit, within a filtering unit with dedicated hardware within the processor, or by a general-purpose digital signal processor (DSP). By using existing units within the processor, little or no modification is required to the processor in order to achieve a substantially improved performance.