Abstract: A processing space comprises an array of transistors empowered by forming connections through circuit pass transistors to power and data input/output means and connections therebetween through signal pass transistors. By structuring the needed circuits at the site(s) of the data the von Neumann bottleneck is eliminated, which increases the computing power of the apparatus substantially, thus to enable non-stop Information Processing on steady streams of data and code, with no repetitive instruction and data transfers required. That code will identify the physical locations of every transistor in the processing space, and will enable only the pass transistors therein needed to structure the circuits of any arithmetical/logical algorithm in a processing space of any size, speed, and level of computer power. By joining one processing space to another the apparatus also exhibits super-scalability.

Abstract: A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed.

Abstract: A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed.