Patents by Inventor William T. Chen
William T. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10916429Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.Type: GrantFiled: December 5, 2019Date of Patent: February 9, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Patent number: 10886263Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: GrantFiled: September 29, 2017Date of Patent: January 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20200111671Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10535521Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: GrantFiled: March 8, 2019Date of Patent: January 14, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10515806Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: GrantFiled: March 8, 2019Date of Patent: December 24, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206683Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206684Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10276382Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: GrantFiled: June 6, 2017Date of Patent: April 30, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Publication number: 20190103386Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: William T. CHEN, John Richard HUNT, Chih-Pin HUNG, Chen-Chao WANG, Chih-Yi HUANG
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Publication number: 20190088506Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.Type: ApplicationFiled: November 6, 2018Publication date: March 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Bernd Karl APPELT, Kay Stefan ESSIG, William T. CHEN, Yuan-Chang SU
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20180047571Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: ApplicationFiled: June 6, 2017Publication date: February 15, 2018Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Publication number: 20160218021Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 ?m.Type: ApplicationFiled: January 27, 2015Publication date: July 28, 2016Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Bernd Karl APPELT, Kay Stefan ESSIG, William T. CHEN, Yuan-Chang SU
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Patent number: 8399776Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.Type: GrantFiled: September 18, 2009Date of Patent: March 19, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Bernd Karl Appelt, William T Chen, Calvin Cheung, Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee
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Publication number: 20100288541Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.Type: ApplicationFiled: September 18, 2009Publication date: November 18, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Bernd Karl APPELT, William T. CHEN, Calvin CHEUNG, Shih-Fu HUANG, Yuan-Chang SU, Chia-Cheng CHEN, Ta-Chun LEE
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Patent number: 7227268Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.Type: GrantFiled: October 29, 2004Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
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Patent number: 7026012Abstract: A method of forming a metallic feature on a substrate, comprising the steps of: providing a stamp having a raised region; depositing catalytic particles on a selected area of the stamp, including the raised region thereof; providing a substrate; applying the stamp to the substrate, such that the raised region of the stamp causes a corresponding indented region in the substrate and at least some of the catalytic particles are transferred to a selected area of the substrate; and plating the selected area of the substrate.Type: GrantFiled: February 22, 2002Date of Patent: April 11, 2006Assignee: Agency for Science, Technology and ResearchInventors: William T. Chen, Peter M. Moran
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Patent number: 6863936Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilised catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.Type: GrantFiled: December 18, 2001Date of Patent: March 8, 2005Assignee: Agency for Science, Technology and ResearchInventors: William T. Chen, Peter M. Moran, Harvey M. Phillips
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Patent number: 6829149Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.Type: GrantFiled: August 18, 1997Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
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Publication number: 20020119251Abstract: A method of forming a metallic feature on a substrate, comprising the steps of: providing a stamp having a raised region; depositing catalytic particles on a selected area of the stamp, including the raised region thereof; providing a substrate; applying the stamp to the substrate, such that the raised region of the stamp causes a corresponding indented region in the substrate and at least some of the catalytic particles are transferred to a selected area of the substrate; and plating the selected area of the substrate.Type: ApplicationFiled: February 22, 2002Publication date: August 29, 2002Inventors: William T. Chen, Peter M. Moran
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Publication number: 20020076497Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilized catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.Type: ApplicationFiled: December 18, 2001Publication date: June 20, 2002Applicant: INSTITUTE OF MATERIALS RESEARCH AND ENGINEERINGInventors: William T. Chen, Peter M. Moran, Harvey M. Phillips