Patents by Inventor William T. Chen

William T. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10380745
    Abstract: A method and corresponding apparatus for measuring object motion using camera images may include measuring a global optical flow field of a scene. The scene may include target and reference objects captured in an image sequence. Motion of a camera used to capture the image sequence may be determined relative to the scene by measuring an apparent, sub-pixel motion of the reference object with respect to an imaging plane of the camera. Motion of the target object corrected for the camera motion may be calculated based on the optical flow field of the scene and on the apparent, sub-pixel motion of the reference object with respect to the imaging plane of the camera. Embodiments may enable measuring vibration of structures and objects from long distance in relatively uncontrolled settings, with or without accelerometers, with high signal-to-noise ratios.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 13, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Oral Buyukozturk, William T. Freeman, Frederic Durand, Myers Abraham Davis, Neal Wadhwa, Justin G. Chen
  • Publication number: 20190206683
    Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the sec
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Publication number: 20190206684
    Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Patent number: 10276382
    Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 30, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Publication number: 20190103386
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: William T. CHEN, John Richard HUNT, Chih-Pin HUNG, Chen-Chao WANG, Chih-Yi HUANG
  • Publication number: 20190088506
    Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl APPELT, Kay Stefan ESSIG, William T. CHEN, Yuan-Chang SU
  • Publication number: 20180047571
    Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.
    Type: Application
    Filed: June 6, 2017
    Publication date: February 15, 2018
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Publication number: 20160218021
    Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 ?m.
    Type: Application
    Filed: January 27, 2015
    Publication date: July 28, 2016
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl APPELT, Kay Stefan ESSIG, William T. CHEN, Yuan-Chang SU
  • Patent number: 8399776
    Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 19, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, William T Chen, Calvin Cheung, Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee
  • Publication number: 20100288541
    Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.
    Type: Application
    Filed: September 18, 2009
    Publication date: November 18, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl APPELT, William T. CHEN, Calvin CHEUNG, Shih-Fu HUANG, Yuan-Chang SU, Chia-Cheng CHEN, Ta-Chun LEE
  • Patent number: 7227268
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Patent number: 7026012
    Abstract: A method of forming a metallic feature on a substrate, comprising the steps of: providing a stamp having a raised region; depositing catalytic particles on a selected area of the stamp, including the raised region thereof; providing a substrate; applying the stamp to the substrate, such that the raised region of the stamp causes a corresponding indented region in the substrate and at least some of the catalytic particles are transferred to a selected area of the substrate; and plating the selected area of the substrate.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: April 11, 2006
    Assignee: Agency for Science, Technology and Research
    Inventors: William T. Chen, Peter M. Moran
  • Patent number: 6863936
    Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilised catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 8, 2005
    Assignee: Agency for Science, Technology and Research
    Inventors: William T. Chen, Peter M. Moran, Harvey M. Phillips
  • Patent number: 6829149
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Publication number: 20020119251
    Abstract: A method of forming a metallic feature on a substrate, comprising the steps of: providing a stamp having a raised region; depositing catalytic particles on a selected area of the stamp, including the raised region thereof; providing a substrate; applying the stamp to the substrate, such that the raised region of the stamp causes a corresponding indented region in the substrate and at least some of the catalytic particles are transferred to a selected area of the substrate; and plating the selected area of the substrate.
    Type: Application
    Filed: February 22, 2002
    Publication date: August 29, 2002
    Inventors: William T. Chen, Peter M. Moran
  • Publication number: 20020076497
    Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilized catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 20, 2002
    Applicant: INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING
    Inventors: William T. Chen, Peter M. Moran, Harvey M. Phillips
  • Patent number: 6358627
    Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: March 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Joseph A. Benenati, Claude L. Bertin, William T. Chen, Thomas E. Dinan, Wayne F. Ellis, Wayne J. Howell, John U. Knickerbocker, Mark V. Pierson, William R. Tonti, Jerzy M. Zalesinski
  • Patent number: 6353182
    Abstract: The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTE's is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTE's reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: March 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
  • Patent number: 6258627
    Abstract: An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Joseph A. Benenati, William T. Chen, Lisa A. Fanti, Wayne J. Howell, John U. Knickerbocker
  • Patent number: 6255599
    Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: July 3, 2001
    Assignee: IBM
    Inventors: Chi Shih Chang, William T. Chen, Ajit Trivedi