Abstract: A system and methods for capacity planning of electronic systems storage are provided. Features include a non-invasive data discovery and collection mechanism, an adaptive grouping mechanism, a flexible analysis mechanism, predictive modeling and forecasting mechanisms, and a business metric and correlation mechanism. A discovery engine that ascertains the availability of collectable entities. A collection engine in turn gathers information from and about entities discovered by the discovery engine. A grouping module groups together entities according to parameters specified by the user. An analysis and forecasting module allows a user to create, modify and save forecast scenarios from which a model is generated by a modeling module. Correlations can be identified between specified key business metrics and historical data. Once a model has been created, a forecast is generated and can then be analyzed using Bold Freehand Extrapolation, time-series analysis, and business trend-based forecasting.

Abstract: A system and methods for capacity planning of electronic systems storage are provided. Features include a non-invasive data discovery and collection mechanism, an adaptive grouping mechanism, a flexible analysis mechanism, predictive modeling and forecasting mechanisms, and a business metric and correlation mechanism. A discovery engine that ascertains the availability of collectable entities. A collection engine in turn gathers information from and about entities discovered by the discovery engine. A grouping module groups together entities according to parameters specified by the user. An analysis and forecasting module allows a user to create, modify and save forecast scenarios from which a model is generated by a modeling module. Correlations can be identified between specified key business metrics and historical data. Once a model has been created, a forecast is generated and can then be analyzed using Bold Freehand Extrapolation, time-series analysis, and business trend-based forecasting.

Abstract: An apparatus and method for improving the input/output performance of a redundant storage array system. The present invention provides a "special parity" cache within the controller for a redundant storage array system, and means for determining and caching a quantity known as the "remaining redundancy row parity" (RRR-parity) block. The RRR-parity block is equal to the old parity block of a redundancy row XOR'd with an old data block being read from the same redundancy row. By caching RRR-parity blocks, Write-intensive storage unit operations can be reduced by up to three input/output accesses.

Abstract: An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repeater component and an environment monitoring component. The environment monitoring component has a standard bus interface and is selectably coupled to the standard interface bus, and hence to a host processor. The host interface transceiver is coupled by means of a standard bus to the host processor, and is also selectably coupled to a drive interface transceiver by means of the standard bus. The drive interface transceiver is coupled by the standard bus to one or more storage devices. The host adapter is selectably switchable between two modes, such that either the drive interface transceiver is coupled through the host interface transceiver to the host processor, or the environment monitoring component is coupled to the host processor.

Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: A special-purpose, microprogrammed digital subsystem sequences through stored lists of microinstructions to produce various control signals. In response to address signals provided by an address generator, the microinstructions are accessed in pairs: A primary microinstruction and a branch or target microinstruction. For the most part, only the primary microinstruction is decoded and executed. However, certain of the ones of primary microinstructions are of the type that require a decision to be made, and the microinstruction stream branches to one of two choices depending upon the outcome of the decision. The target microinstruction forms the first microinstruction of one of the available microinstruction branches, and, if this branch is taken, is executed in parallel with the branch to avoid time penalties. An additional aspect of the invention is that the address generator, which provides address signals to a memory that stores the microinstructions, is capable of functioning as a timer circuit.

Abstract: An apparatus determines the order of data communication between a plurality of peripheral devices that wish to do so and a central processor unit. Determination is made according to one of a number of selectable priority schedules. The apparatus is modifiable by programmed control so that certain of the peripheral devices can have their priorities reconfigured depending upon changing circumstances.