Abstract: Various aspects of the disclosed technology relate to the generation for test purposes of test traffic, in a manner compliant with advanced flow control.

Abstract: Various aspects of the disclosed technology relate to the generation for test purposes of test traffic, in a manner compliant with advanced flow control.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Embodiments of the invention relate to generating simulated network traffic. In some embodiments, simulated network traffic may be generated using a specification of a sequence of frames to be transmitted from the network testing device. The specification may specify at least two frames including a first frame and a second frame. The specification may further specify a first interframe gap associated with the first frame and a second interframe gap, having a different length from the first interframe gap, associated with the second frame. In some embodiments, the specification may specify an interframe gap for each frame in the sequence of frames. This information may be used to determine the relative transmit time of each frame to be transmitted. Because the specification identifies an interframe gap for each frame in the sequence, in some embodiments, multi-frame burst network traffic may be generated.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: Embodiments of the invention relate to generating simulated network traffic. In some embodiments, simulated network traffic may be generated using a specification of a sequence of frames to be transmitted from the network testing device. The specification may specify at least two frames including a first frame and a second frame. The specification may further specify a first interframe gap associated with the first frame and a second interframe gap, having a different length from the first interframe gap, associated with the second frame. In some embodiments, the specification may specify an interframe gap for each frame in the sequence of frames. This information may be used to determine the relative transmit time of each frame to be transmitted. Because the specification identifies an interframe gap for each frame in the sequence, in some embodiments, multi-frame burst network traffic may be generated.

Abstract: Timestamp information can be placed in a frame that includes a first portion processable at a selected layer of a protocol stack and a second portion processable at a lower protocol layer of the protocol stack subsequently to the processing of the first portion, wherein the first portion is contained within the second portion and wherein a numerically computed error detection code for the second portion is computed during processing of the second portion. A timestamp signature having a timestamp subfield of initialized data and a corrector subfield of initialized data is embedded in the first portion during processing thereof at the selected protocol layer. A numerical constant functionally equivalent to the numerically computed error detection code is determinable from the initialized data in the timestamp subfield and the corrector subfield. The data in said timestamp subfield is modified with timestamp information subsequently to processing of the second portion at the lower protocol layer.

Abstract: Processor methods and apparatus for adaptable network processing having speed advantages often associated with hardware implementations of network processing code or logic, as is often achieved using ASICs, for example, but at the same time having reconfigurability advantages often associated with software implementations of this code or logic. Methods and apparatus are described for adaptable hardware devices, such as a field programmable gate array (FPGA) or a circuit using FPGAs, to execute network processing code or logic. Methods and apparatus are described for using a software based device to program adaptable hardware devices to implement desired network processing code or logic.

Abstract: A real time digital filter with its transfer function being matched to a particular signal plus noise condition in a manner that causes the transfer function to adapt to changing signal plus noise conditions. A transversal type of digital filter is disclosed. A general purpose computer calculates coefficients of the filter by continuously monitoring the input signal plus noise in order to maintain the filter's transfer function at an optimum level in view of changing noise conditions.