Abstract: Generally discussed herein are systems, devices, and methods for device verification. A method can include providing, by test equipment (TE), electrical stimulus consistent with a challenge of a challenge response pair (CRP) to a physical unclonable function (PUF) of a device under test (DUT), receiving, by the TE and from the DUT, a response to the electrical stimulus, comparing, by the TE, the provided response to responses to CRPs in a database including PUF CRPs associated with a device identification and a device type, and validating the identity of the DUT when the response of the PUF to the electrical stimulus matches the response of the CRP or invalidating the identity of the electrical device when the response of the PUF does not match the response of the CRP.

Abstract: Generally discussed herein are systems, devices, and methods for device verification. A method can include providing, by test equipment (TE), electrical stimulus consistent with a challenge of a challenge response pair (CRP) to a physical unclonable function (PUF) of a device under test (DUT), receiving, by the TE and from the DUT, a response to the electrical stimulus, comparing, by the TE, the provided response to responses to CRPs in a database including PUF CRPs associated with a device identification and a device type, and validating the identity of the DUT when the response of the PUF to the electrical stimulus matches the response of the CRP or invalidating the identity of the electrical device when the response of the PUF does not match the response of the CRP.

Abstract: Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

Abstract: Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

Abstract: A system for detecting changes to circuitry includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuitry, operational data of the circuitry, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of a first set of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; periodically update the dynamic fingerprint according to successive sets of the captured data; and compare the updated dynamic fingerprint to a previous dynamic fingerprint, to detect the changes to the circuitry.

Abstract: A system for authenticating a circuit includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuit, operational data of the circuit, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; and output the dynamic fingerprint as a physically unclonable function (PUF) of the circuit.

Abstract: This disclosure provides for implementing a firmware security interface within a field-programmable gate array (FPGA) for communicating between secure and non-secure environments executable within the FPGA. A security monitor is implemented within the programmable logic of the FPGA as a soft core processor and the firmware security interface modifies one or more functions of the security monitor. The modifications to the security monitor include establishing a timer “heartbeat” within the FPGA to ensure that the FPGA invokes a secure environment and raising an alarm should the FPGA fail to invoke such environment.

Abstract: A system for authenticating a circuit includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuit, operational data of the circuit, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; and output the dynamic fingerprint as a physically unclonable function (PUF) of the circuit.

Abstract: A system for detecting changes to circuitry includes: a processor; and a memory, and the memory has stored thereon instructions that, when executed by the processor, cause the processor to: periodically measure physical characteristic data of the circuitry, operational data of the circuitry, and environmental data; periodically capture the measured data; generate a dynamic fingerprint based on an aggregation of a first set of the captured data, and the dynamic fingerprint is a compound data structure encapsulating the aggregated data; associate metadata with the dynamic fingerprint; periodically update the dynamic fingerprint according to successive sets of the captured data; and compare the updated dynamic fingerprint to a previous dynamic fingerprint, to detect the changes to the circuitry.

Abstract: This disclosure provides for implementing a firmware security interface within a field-programmable gate array (FPGA) for communicating between secure and non-secure environments executable within the FPGA. A security monitor is implemented within the programmable logic of the FPGA as a soft core processor and the firmware security interface modifies one or more functions of the security monitor. The modifications to the security monitor include establishing a timer “heartbeat” within the FPGA to ensure that the FPGA invokes a secure environment and raising an alarm should the FPGA fail to invoke such environment.

Abstract: According to one embodiment, an imaging system includes an interface, a plurality of filters, and a processor. The interface receives data blocks. The processor associates each data block with a processing step list that represents a filter chain that has at least a subset of the filters coupled in sequence. The processor filters each data block according to the filter chain represented by the associated processing step list.

Abstract: According to one embodiment, generating images according to intersection points includes obtaining samples of signals from transmitter-receiver pairs. A transmitter-receiver pair is configured to transmit a signal and receive the signal reflected by an object. Intersection points are determined, where an intersection point indicates an intersection for integer multiples of a sample-time distance. A subset of samples corresponding to the intersection points is selected. Image data is generated from the selected subset of samples, where the image data is used to generate an image of the object.

Abstract: According to one embodiment, an imaging system includes an interface, a plurality of filters, and a processor. The interface receives data blocks. The processor associates each data block with a processing step list that represents a filter chain that has at least a subset of the filters coupled in sequence. The processor filters each data block according to the filter chain represented by the associated processing step list.

Abstract: According to one embodiment, generating images according to intersection points includes obtaining samples of signals from transmitter-receiver pairs. A transmitter-receiver pair is configured to transmit a signal and receive the signal reflected by an object. Intersection points are determined, where an intersection point indicates an intersection for integer multiples of a sample-time distance. A subset of samples corresponding to the intersection points is selected. Image data is generated from the selected subset of samples, where the image data is used to generate an image of the object.

Abstract: The storage and retrieval of cryptographic key materials from a storage database utilizes a limited one-way function to create computational barriers. The limited one-way function is asymmetric in nature, in terms of work to compute and work to invert, to store and retrieve encryption keys. The limited one-way function is not intractable, but alternatively, there is some measurable difference in the amount of work required to invert a stored encryption key, compared to the work required for a calculation of the output of the one-way function for storage of an encryption key in a database.

Abstract: An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.

Abstract: A circuit for the implementation of modular multiplication of numbers comprises an alternative formation of the algorithm first proposed by R. C. Montgomery. The modified Montgomery algorithm is implemented in one of a plurality of circuits comprising full adders, half adders, registers and gates.

Abstract: A multi-purpose, transmissive paper sensor includes a light beam projector and light detector having an analog output signal. Changes in the output signal from an open loop condition indicate the presences of at least one print medium being in the field-of-view of the sensor. Output signals indicative of print media leading edge, trailing edge, and number of sheets interrupting the light beam provide improved print media transport control for hard copy apparatus.

Abstract: An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.

Abstract: An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.