Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.

Abstract: Simple and cost-effective methods for forming tall, high-aspect ratio structures in a material layer comprising a first layer of a image-reversal-type photo-sensitive material and a second layer of a positive-type photo-sensitive material is disclosed. The layers are formed, exposed to actinic radiation, and developed such that the formation, exposure, and development of the second layer does not substantially modify or destroy the patterns formed in the first layer. In one embodiment, the first layer is exposed to actinic radiation through a first mask comprising the complimentary image, or negative, of a desired high-aspect ratio structure. The image in the first layer is then reversed by heating to an elevated temperature and subsequently blank flood exposure of actinic radiation. A second layer of a positive type photo-sensitive material chemically compatible with the IRP layer is then formed over the first layer.

Abstract: Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures.