Abstract: A device for differential-mode processing of an incident voltage relative to a reference voltage includes a differential circuit including a voltage/current conversion block having a differential input, designed to receive the incident voltage at a first input and the reference voltage at a second input. A current amplification block includes a gain module and a current subtraction module. A current/voltage conversion block includes an operational amplifier with differential transimpedance supplied with a common-mode voltage, receiving the two currents output from the amplification block at its input, and delivering two calibrated opposing voltages at its output that are centered around the common-mode voltage.

Abstract: Modified colorants are made from a modifying agent, such as platelet alumina, and a colorant. The colorant may be fixed to the surface of the modifying agent, optionally with a surface treatment. The colorant may not completely coat the surface of the modifying agent, and the edge of the modifying agent may be substantially free of colorant. The modified colorants may be used in cosmetic products.

Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.

Abstract: A device for differential-mode processing of an incident voltage relative to a reference voltage includes a differential circuit including a voltage/current conversion block having a differential input, designed to receive the incident voltage at a first input and the reference voltage at a second input. A current amplification block includes a gain module and a current subtraction module. A current/voltage conversion block includes an operational amplifier with differential transimpedance supplied with a common-mode voltage, receiving the two currents output from the amplification block at its input, and delivering two calibrated opposing voltages at its output that are centered around the common-mode voltage.

Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.

Abstract: A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract: The present invention relates to a converting device for converting an analog input signal Vin into a digital output signal OUT, whose gain is equal to the ratio between the values of the output and input signals, comprising: a resistor ladder LAD intended to generate reference voltages, and a plurality of amplifiers A, intended to compare the input signal Vin with the reference voltages. According to the invention, the converting device includes adjusting means for making the gain of the amplifiers and the gain of the converting device proportional to each other. The invention enables to ensure that the differential non-linearity of the converting device remains constant and thus that its behavior does not change when its gain varies.

Abstract: This device includes a main signal path in which a capacitor is included upstream of an analog/digital converter in which a conversion is triggered by a clock. According to the invention, the output of the analog/digital converter is connected to inputs of several threshold detectors which have positive detection thresholds in a progression proportional to consecutive powers of two, and several other threshold detectors which have negative detection thresholds which also progress proportionally to consecutive powers of two, which threshold detectors control current generators whose currents are added together into the capacitor.