Abstract: A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract: A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract: A valve assembly includes a body having a bore and a valve received within the bore for movement between an open position and a closed position. First and second sealing members are secured for movement with the valve and are positioned between the valve and the body such that an internal fluid pressure within the bore is applied to a first side of the sealing members and a common reference pressure is applied to a second side. An axial force imparted on the valve adjacent the second sealing member is less than an axial force imparted on the valve adjacent the first sealing member. A resiliently compressible member is positioned to bias the valve toward the normally open position. The valve is moved to the closed position when the internal fluid pressure exceeds a predetermined pressure and returns to the open position when the internal fluid pressure is substantially less than the predetermined pressure.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time.

Abstract: A method, apparatus, and article of manufacture for monitoring performance of an application or a system program executed by a multithreaded processor arranged and configured to process a plurality of threads and facilitate thread switch. The low-level invisible events, such as cache misses, or other events of interest of an application or a system program, are detected and recorded by using a software monitor program running on a thread of the multithreaded processor via thread switching techniques. The monitoring thread gains control once a selected event is detected while executing the application or system program, and it relinquishes the control after completing the recording of the selected event. The recorded information allows one to dynamically profile the application or the system program and to provide insight into the performance characteristics of the application or the system program.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Abstract: A multithreaded processor and a method for performance monitoring within a multithreaded processor are described. According to the present invention, execution circuitry within the multithreaded processor executes instructions in an active thread among first and second concurrent threads, while buffering circuitry buffers instructions and/or data of an inactive one of the first and second concurrent threads. Thread switch logic in the multithreaded processor switches threads by activating the inactive thread and inactivating the active thread. The operation of the multithreaded processor is monitored by a performance monitor, which records occurrences of an event generated by switching threads.

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.

Abstract: Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize instruction match register/execution control register (IMR/ECR) pairs to first identify known problematic instructions and to then alter control of the microprocessor in a preselected manner when processing each problematic instruction. The invention contemplates the use of numerous control options for altering control of the microprocessor.