Patents by Inventor William Thomas Lynch
William Thomas Lynch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7958388Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.Type: GrantFiled: June 1, 2009Date of Patent: June 7, 2011Assignee: Parallel Iron LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 7941595Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.Type: GrantFiled: May 15, 2007Date of Patent: May 10, 2011Assignee: Ring Technology Enterprises of Texas, LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 7808844Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.Type: GrantFiled: May 29, 2007Date of Patent: October 5, 2010Assignee: Ring Technology Enterprises os Texas, LLCInventors: William Thomas Lynch, David James Herbison
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Patent number: 7707351Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.Type: GrantFiled: October 31, 2002Date of Patent: April 27, 2010Assignee: Ring Technology Enterprises of Texas, LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Publication number: 20090240976Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.Type: ApplicationFiled: June 1, 2009Publication date: September 24, 2009Inventors: Melvin James BULLEN, Steven Louis DODD, William Thomas LYNCH, David James HERBISON
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Patent number: 7543177Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.Type: GrantFiled: February 26, 2007Date of Patent: June 2, 2009Assignee: Ring Technology Enterprises, LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 7415565Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller, and a switch. The switch is capable of reading a data request including a data block identifier and routing the data request and any associated data through the switch on the basis of this data block identifier, such that a data request may be routed to a memory section. The section controller, in response, determines the addresses in the memory devices storing the requested data, and it transfers these addresses to those memory devices storing the requested data.Type: GrantFiled: October 31, 2002Date of Patent: August 19, 2008Assignee: Ring Technology Enterprises, LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 7313035Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.Type: GrantFiled: January 10, 2005Date of Patent: December 25, 2007Assignee: Ring Technology Enterprises, LLC.Inventors: William Thomas Lynch, David James Herbison
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Patent number: 7197662Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from, service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.Type: GrantFiled: October 31, 2002Date of Patent: March 27, 2007Assignee: Ring Technology Enterprises, LLCInventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 6879526Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.Type: GrantFiled: October 31, 2002Date of Patent: April 12, 2005Assignee: Ring Technology Enterprises LLCInventors: William Thomas Lynch, David James Herbison
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Publication number: 20040088477Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Inventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Publication number: 20040085818Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Inventors: William Thomas Lynch, David James Herbison
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Publication number: 20040088393Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from, service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Inventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Publication number: 20040088514Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller, and a switch. The switch is capable of reading a data request including a data block identifier and routing the data request and any associated data through the switch on the basis of this data block identifier, such that a data request may be routed to a memory section. The section controller, in response, determines the addresses in the memory devices storing the requested data, and it transfers these addresses to those memory devices storing the requested data.Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Inventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
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Patent number: 4091360Abstract: In MOS circuitry, such as a dynamic MOS random access memory, precharge circuitry, consisting of six p-channel MOS transistors and a seventh p-channel MOS transistor connected as a capacitor, facilitates a two step charging process that initially lowers the potential of a first circuit node from a high potential to a value approximately one threshold voltage above an available low level power supply potential and then further lowers the potential of the circuit node to a value below that of the available low level power supply potential. A single voltage pulse and the complement thereof are the only input signals required. Normal threshold voltage losses of MOS transistors can thus be effectively eliminated and noise margins thereby improved.Type: GrantFiled: September 1, 1976Date of Patent: May 23, 1978Assignee: Bell Telephone Laboratories, IncorporatedInventor: William Thomas Lynch