Patents by Inventor William Thomas Motsiff
William Thomas Motsiff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7704876Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: August 30, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Patent number: 7300867Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: July 5, 2005Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Patent number: 6958540Abstract: Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: GrantFiled: June 23, 2003Date of Patent: October 25, 2005Assignee: International Business Machines CorporationInventors: Jeffrey Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Publication number: 20040262764Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.Type: ApplicationFiled: June 23, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, Edward Cooney, III, Anthony Stamper, William Thomas Motsiff, Michael Lane, Andrew Simon
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Patent number: 6605526Abstract: A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.Type: GrantFiled: March 16, 2000Date of Patent: August 12, 2003Assignee: International Business Machines CorporationInventors: Wayne John Howell, Ronald Lee Mendelson, William Thomas Motsiff, Jean-Guy Quintal, Sylvain Ouimet
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Patent number: 6440834Abstract: A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.Type: GrantFiled: April 6, 2001Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, William Thomas Motsiff, Jed Hickory Rankin
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Patent number: 6340630Abstract: A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip.Type: GrantFiled: March 28, 2000Date of Patent: January 22, 2002Assignee: International Business Machines CorporationInventors: Daniel George Berger, Guy Paul Brouillette, David Hirsch Danovitch, Peter Alfred Gruber, Bruce Lee Humphrey, Michael Liehr, William Thomas Motsiff, Carlos Juan Sambucetti
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Publication number: 20010014509Abstract: A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.Type: ApplicationFiled: April 6, 2001Publication date: August 16, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, William Thomas Motsiff, Jed Hickory Rankin
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Patent number: 6249038Abstract: A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.Type: GrantFiled: June 4, 1999Date of Patent: June 19, 2001Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, William Thomas Motsiff, Jed Hickory Rankin
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Patent number: 6127735Abstract: A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip.Type: GrantFiled: September 25, 1996Date of Patent: October 3, 2000Assignee: International Business Machines CorporationInventors: Daniel George Berger, Guy Paul Brouillette, David Hirsch Danovitch, Peter Alfred Gruber, Bruce Lee Humphrey, Michael Liehr, William Thomas Motsiff, Carlos Juan Sambucetti
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Patent number: 6093630Abstract: The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.Type: GrantFiled: May 18, 1998Date of Patent: July 25, 2000Assignee: International Business Machines CorporationInventors: Robert Michael Geffken, William Thomas Motsiff, Ronald R. Uttecht
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Patent number: 5897336Abstract: An interconnect system that has low alpha particle emission characteristics for use in an electronic device includes a semiconductor chip that has an upper surface and spaced apart electrically resistive bumps positioned on conductive regions of the upper surface, the electrically resistive bumps are made of a composite material of a polymer and metal particles, and a substrate that has conductive regions bonded to the electrically resistive bumps in a bonding process wherein the electrically resistive bumps convert to electrically conductive bumps after the bonding process.Type: GrantFiled: May 28, 1997Date of Patent: April 27, 1999Assignee: International Business Machines CorporationInventors: Guy Paul Brouillette, David Hirsch Danovitch, Michael Liehr, William Thomas Motsiff, Judith Marie Roldan, Carlos Juan Sambucetti, Ravi F. Saraf
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Patent number: 5883435Abstract: The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.Type: GrantFiled: July 25, 1996Date of Patent: March 16, 1999Assignee: International Business Machines CorporationInventors: Robert Michael Geffken, William Thomas Motsiff, Ronald R. Uttecht
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Patent number: 5795819Abstract: A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.Type: GrantFiled: September 9, 1997Date of Patent: August 18, 1998Assignee: International Business Machines CorporationInventors: William Thomas Motsiff, Robert Michael Geffken, Ronald Robert Uttecht
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Patent number: 5731624Abstract: A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.Type: GrantFiled: June 28, 1996Date of Patent: March 24, 1998Assignee: International Business Machines CorporationInventors: William Thomas Motsiff, Robert Michael Geffken, Ronald Robert Uttecht
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Patent number: 5719070Abstract: A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.Type: GrantFiled: October 2, 1996Date of Patent: February 17, 1998Assignee: International Business Machines CorporatonInventors: Herbert Carl Cook, Paul Alden Farrar, Sr., Robert Michael Geffken, William Thomas Motsiff, Adolf Ernest Wirsing