Patents by Inventor William Tien

William Tien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for a cache-coherent interconnect protocol storage device
    Patent number: 12591530
    Abstract: A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 31, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Jimmy Lau, Amir Beygi, Mohammadreza Soltaniyeh, Tinh Lac, Divya Subbanna, Mostafa Aghaee, Dongwan Zhao, William Tien, Varadraj Ninad Sinai Kakodkar, Luis Vitorio Cargnini
  • Device cache engine for a cache-coherent interconnect memory expansion
    Patent number: 12541326
    Abstract: A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: February 3, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Jimmy Lau, Mohammadreza Soltaniyeh, Amir Beygi, Tinh Lac, Divya Subbanna, Mostafa Aghaee, Dongwan Zhao, William Tien, Varadraj Ninad Sinai Kakodkar, Luis Vitorio Cargnini
  • SYSTEMS AND METHODS FOR A CACHE-COHERENT INTERCONNECT PROTOCOL STORAGE DEVICE
    Publication number: 20240311318
    Abstract: A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
    Type: Application
    Filed: November 17, 2023
    Publication date: September 19, 2024
    Inventors: Ramdas P. KACHARE, Jimmy LAU, Amir BEYGI, Mohammadreza SOLTANIYEH, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
  • DEVICE CACHE ENGINE FOR A CACHE-COHERENT INTERCONNECT MEMORY EXPANSION
    Publication number: 20240311049
    Abstract: A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.
    Type: Application
    Filed: November 20, 2023
    Publication date: September 19, 2024
    Inventors: Ramdas P. KACHARE, Jimmy LAU, Mohammadreza SOLTANIYEH, Amir BEYGI, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
  • High voltage transistor with improved driving current
    Publication number: 20070085145
    Abstract: A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side boundary of the first doped region underlies part of the gate electrode. The second doped region is formed within the first doped region adjacent the gate electrode. A gate-side boundary of the second doped region is separated from a closest edge of a gate electrode spacer by a first distance. An isolation region-side boundary of the second doped region is separated from a closest edge of a nearest isolation region by a second distance.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: William Tien, Fu-Hsin Chen, Jui-Wen Lin, You-Kuo Wu