Abstract: The present invention provides a method, computer program product, and distributed data processing system to allow the hardware mechanism of the Internet Protocol Suite Offload Engine (IPSOE) to interpret the iSCSI commands, process the iSCSI commands, and to interpret the iSCSI command completion results with the iSCSI driver. The distributed data processing system comprises endnodes, switches, routers, and links interconnecting the components. The endnodes use send and receive queue pairs to transmit and receive messages. The endnodes segment the message into frames and transmit the frames over the links. The switches and routers interconnect the endnodes and route the frames to the appropriate endnodes. The endnodes reassemble the frames into a message at the destination.

Abstract: A method, computer program product, and distributed data processing system for supporting RNIC (RDMA enabled NIC) switchover and switchback are provided. Using the mechanism provided in the present invention when a planned or unplanned outage occurs on a primary RNIC, all outstanding connections are switched over to an alternate RNIC, and the alternate RNIC continues communication processing. Additionally, using the mechanism provided in the present invention, connections can also be switched back.

Abstract: A method, computer program product, and distributed data processing system for lazy deregistration of memory regions. Specifically, the present invention is directed to memory regions that are written to and from by an Integrated Protocol Suite Offload Engine (IPSOE) in accordance with a preferred embodiment of the present invention. A mechanism is provided for lazy deregistration of memory regions once the region is no longer required for a specific data transfer being carried out by the IPSOE. Rather than deregistering a memory region after a data transfer has been carried out, the memory region remains registered for some selected period of time. After that selected period of time passes, the region is then deregistered. If a second data transfer using this memory region occurs while the memory region is still registered, the registration overhead is avoided for this second data transfer.

Abstract: The present invention provides a method, computer program product, and distributed data processing system for virtualizing the Queue Pairs used by an Internet Protocol Suite Offload Engine (IPSOE). The distributed data processing system comprises end nodes, switches, routers, and links interconnecting the components. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes segment the message into frames and transmit the frames over the links. The switches and routers interconnect the end nodes and route the frames to the appropriate end nodes. The end nodes reassemble the frames into a message at the destination.

Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of the sequential stream of instructions by the first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of the computer system which is determined by a combination of the states of the first and second processing elements.

Abstract: An integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip. As an extension of this basic structure, the invention also contemplates multiprocessor "node" chips in which multiple processors are integrated on a single chip with L2 cache. By integrating the processor and L2 DRAM cache on a single chip, high on-chip bandwidth, reduced latency and higher performance are achieved. A multiprocessor system can be realized in which a plurality of processors with integrated L2 DRAM cache are connected in a loosely coupled multiprocessor system. Alternatively, the single chip technology can be used to implement a plurality of processors integrated on a single chip with an L2 DRAM cache which may be either private or shared. This approach overcomes a number of issues which limit the performance and cost of a memory hierarchy. When the L2 DRAM cache is placed on the same chip as the processor, the time needed for two chip-to-chip crossings is eliminated.

Abstract: Connects a host computer system (such as a mainframe or host server system) to a large multimedia (MM) distribution network having wide scalability without being limited by bandwidth constraints in the host system or in any multimedia controller for controlling "on demand" viewing of movies at a large number of set-top-boxes (STBs) with TV sets. Connected to the host system is a network distribution arrangement comprised of a plurality of multimedia (MM) adapters, each MM adapter containing a plurality of MM controllers, each MM controller being connected to a multiplicity of MM pairs, each MM pair being connected to the network for controlling a direct distribution of movies to a large number of STBs. Each MM pair includes a disk adapter and a network adapter connected by a common MM pair bus for transmitting disk data blocks directly to the STBs. The disk adapter controls and receives data from one or more disk devices. The network adapter sends the disk data to the network.