Patents by Inventor William Todd Smithgall

William Todd Smithgall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121910
    Abstract: In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to receive each of at least one input-data message. The comparing circuit is configured to compare each of the at least one received input-data message to a list of input-data-message identifiers. And the indicator circuit is configured, for each of the at least one input-data message that corresponds to a respective input-data-message identifier, to generate a respective portion of a first status message, the respective portion indicating that the input-data message was received. For example, such computing node can determine the congruency of a received input-data message between coupled redundancy circuits with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Honeywell International Inc.
    Inventors: Brendan Hall, William Todd Smithgall, Paul Frederick Dietrich, Ted Bonk, Kevin Raymond Driscoll
  • Publication number: 20200195490
    Abstract: In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to receive each of at least one input-data message. The comparing circuit is configured to compare each of the at least one received input-data message to a list of input-data-message identifiers. And the indicator circuit is configured, for each of the at least one input-data message that corresponds to a respective input-data-message identifier, to generate a respective portion of a first status message, the respective portion indicating that the input-data message was received. For example, such computing node can determine the congruency of a received input-data message between coupled redundancy circuits with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.
    Type: Application
    Filed: October 11, 2019
    Publication date: June 18, 2020
    Applicant: Honeywell International Inc.
    Inventors: Brendan Hall, William Todd Smithgall, Paul Frederick Dietrich, Ted Bonk, Kevin Raymond Driscoll
  • Patent number: 9769082
    Abstract: Systems and methods for network bandwidth, buffers and timing management using hybrid scheduling of traffic with different priorities and guarantees are provided. In certain embodiments, a method of managing network scheduling and configuration comprises, for each transmitting end station, reserving one exclusive buffer for each virtual link to be transmitted from the transmitting end station; for each receiving end station, reserving exclusive buffers for each virtual link to be received at the receiving end station; and for each switch, reserving a exclusive buffer for each virtual link to be received at an input port of the switch. The method further comprises determining if each respective transmitting end station, receiving end station, and switch has sufficient capability to support the reserved buffers; and reporting buffer infeasibility if each respective transmitting end station, receiving end station, and switch does not have sufficient capability to support the reserved buffers.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 19, 2017
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Patent number: 9769075
    Abstract: Systems and methods for interference cognizant network scheduling are provided. In certain embodiments, a method of scheduling communications in a network comprises identifying a bin of a global timeline for scheduling an unscheduled virtual link, wherein a bin is a segment of the timeline; identifying a pre-scheduled virtual link in the bin; and determining if the pre-scheduled and unscheduled virtual links share a port. In certain embodiments, if the unscheduled and pre-scheduled virtual links don't share a port, scheduling transmission of the unscheduled virtual link to overlap with the scheduled transmission of the pre-scheduled virtual link; and if the unscheduled and pre-scheduled virtual links share a port: determining a start time delay for the unscheduled virtual link based on the port; and scheduling transmission of the unscheduled virtual link in the bin based on the start time delay to overlap part of the scheduled transmission of the pre-scheduled virtual link.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 19, 2017
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Patent number: 9762501
    Abstract: Systems and methods for systematic hybrid network scheduling for multiple traffic classes with host timing and phase constraints are provided. In certain embodiments, a method of scheduling communications in a network comprises scheduling transmission of virtual links pertaining to a first traffic class on a global schedule to coordinate transmission of the virtual links pertaining to the first traffic class across all transmitting end stations on the global schedule; and scheduling transmission of each virtual link pertaining to a second traffic class on a local schedule of the respective transmitting end station from which each respective virtual link pertaining to the second traffic class is transmitted such that transmission of each virtual link pertaining to the second traffic class is coordinated only at the respective end station from which each respective virtual link pertaining to the second traffic class is transmitted.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 12, 2017
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160294720
    Abstract: Systems and methods for systematic hybrid network scheduling for multiple traffic classes with host timing and phase constraints are provided. In certain embodiments, a method of scheduling communications in a network comprises scheduling transmission of virtual links pertaining to a first traffic class on a global schedule to coordinate transmission of the virtual links pertaining to the first traffic class across all transmitting end stations on the global schedule; and scheduling transmission of each virtual link pertaining to a second traffic class on a local schedule of the respective transmitting end station from which each respective virtual link pertaining to the second traffic class is transmitted such that transmission of each virtual link pertaining to the second traffic class is coordinated only at the respective end station from which each respective virtual link pertaining to the second traffic class is transmitted.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160294721
    Abstract: Systems and methods for network bandwidth, buffers and timing management using hybrid scheduling of traffic with different priorities and guarantees are provided. In certain embodiments, a method of managing network scheduling and configuration comprises, for each transmitting end station, reserving one exclusive buffer for each virtual link to be transmitted from the transmitting end station; for each receiving end station, reserving exclusive buffers for each virtual link to be received at the receiving end station; and for each switch, reserving a exclusive buffer for each virtual link to be received at an input port of the switch. The method further comprises determining if each respective transmitting end station, receiving end station, and switch has sufficient capability to support the reserved buffers; and reporting buffer infeasibility if each respective transmitting end station, receiving end station, and switch does not have sufficient capability to support the reserved buffers.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Publication number: 20160294697
    Abstract: Systems and methods for interference cognizant network scheduling are provided. In certain embodiments, a method of scheduling communications in a network comprises identifying a bin of a global timeline for scheduling an unscheduled virtual link, wherein a bin is a segment of the timeline; identifying a pre-scheduled virtual link in the bin; and determining if the pre-scheduled and unscheduled virtual links share a port. In certain embodiments, if the unscheduled and pre-scheduled virtual links don't share a port, scheduling transmission of the unscheduled virtual link to overlap with the scheduled transmission of the pre-scheduled virtual link; and if the unscheduled and pre-scheduled virtual links share a port: determining a start time delay for the unscheduled virtual link based on the port; and scheduling transmission of the unscheduled virtual link in the bin based on the start time delay to overlap part of the scheduled transmission of the pre-scheduled virtual link.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Srivatsan Varadarajan, Brendan Hall, William Todd Smithgall, Ted Bonk, Benjamin F. DeLay
  • Patent number: 8634305
    Abstract: Methods and apparatus are provided for evaluating the performance of a Time Triggered Ethernet (TTE) system employing Time Triggered (TT) communication. A real TTE system under test (SUT) having real input elements communicating using TT messages with output elements via one or more first TTE switches during a first time interval schedule established for the SUT. A simulation system is also provided having input simulators that communicate using TT messages via one or more second TTE switches with the same output elements during a second time interval schedule established for the simulation system. The first and second time interval schedules are off-set slightly so that messages from the input simulators, when present, arrive at the output elements prior to messages from the analogous real inputs, thereby having priority over messages from the real inputs and causing the system to operate based on the simulated inputs when present.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Honeywell International Inc.
    Inventors: William Todd Smithgall, Brendan Hall, Srivatsan Varadarajan
  • Patent number: 8503484
    Abstract: A node comprises a host computer operable to execute application tasks and to transmit data; a local time-triggered Ethernet switch operable to enforce temporal constraints on time-triggered data; and a time-triggered Ethernet controller coupled to the local time-triggered Ethernet switch and operable to be coupled to a time-triggered Ethernet switch in each of a plurality of other control nodes. The time-triggered Ethernet controller is further operable to communicate with the plurality of other control nodes to synchronize a local clock to establish a global time base and to provide a signal to the host computer for the host computer to synchronize execution of the application tasks by the host computer with the execution of application tasks in each of the plurality of other control nodes.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: August 6, 2013
    Assignee: Honeywell International Inc.
    Inventors: Ted Bonk, William Todd Smithgall, Mitch Fletcher, Greg Carlucci
  • Publication number: 20130058217
    Abstract: Methods and apparatus are provided for evaluating the performance of a Time Triggered Ethernet (TTE) system employing Time Triggered (TT) communication. A real TTE system under test (SUT) having real input elements communicating using TT messages with output elements via one or more first TTE switches during a first time interval schedule established for the SUT. A simulation system is also provided having input simulators that communicate using TT messages via one or more second TTE switches with the same output elements during a second time interval schedule established for the simulation system. The first and second time interval schedules are off-set slightly so that messages from the input simulators, when present, arrive at the output elements prior to messages from the analogous real inputs, thereby having priority over messages from the real inputs and causing the system to operate based on the simulated inputs when present.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: William Todd Smithgall, Brendan Hall, Srivatsan Varadarajan
  • Publication number: 20100183016
    Abstract: A node comprises a host computer operable to execute application tasks and to transmit data; a local time-triggered Ethernet switch operable to enforce temporal constraints on time-triggered data; and a time-triggered Ethernet controller coupled to the local time-triggered Ethernet switch and operable to be coupled to a time-triggered Ethernet switch in each of a plurality of other control nodes.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Ted Bonk, William Todd Smithgall, Mitch Fletcher, Greg Carlucci