Patents by Inventor William Tonti
William Tonti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8575718Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.Type: GrantFiled: November 4, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Michael J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
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Publication number: 20130001789Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, Veeraraghavan S. Basker, William Tonti, Keith K. H. Wong
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Publication number: 20120280356Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
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Patent number: 8288276Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.Type: GrantFiled: December 30, 2008Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Veeraraghavan S. Basker, William Tonti, Keith Kwong Hon Wong
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Patent number: 8232177Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.Type: GrantFiled: September 30, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Wagdi Abadeer, Lilian Kamal, legal representative, Kiran V Chatty, Robert J Gauthier, Jr., Jed H Rankin, Robert R Robison, William Tonti
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Publication number: 20120049321Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Abou-Khalil, Robert J. Gauthier, JR., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
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Patent number: 8101505Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.Type: GrantFiled: June 9, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
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Publication number: 20110073985Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: International Business Machines CorporationInventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
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Patent number: 7772649Abstract: A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.Type: GrantFiled: February 25, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Louis C. Hsu, Jack A. Mandelman, Carl Radens, William Tonti
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Patent number: 7768130Abstract: A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.Type: GrantFiled: November 14, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Tonti, Chih-Chao Yang
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Publication number: 20100164111Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Veeraraghavan S. Basker, William Tonti, Keith Kwong Hon Wong
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Patent number: 7728371Abstract: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.Type: GrantFiled: September 19, 2007Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Louis C Hsu, Jack A. Mandelman, William Tonti
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Publication number: 20090302416Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Applicant: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Robert J. Gauthier, JR., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
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Publication number: 20090212362Abstract: A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Louis C. Hsu, Jack A. Mandelman, Carl Radens, William Tonti
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Patent number: 7521776Abstract: Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.Type: GrantFiled: December 29, 2006Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, Toshiharu Furukawa, Charles Koburger, III, Jack A. Mandelman, William Tonti
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Publication number: 20090072290Abstract: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Louis C. Hsu, Jack A. Mandelman, William Tonti
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Patent number: 7462547Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.Type: GrantFiled: December 4, 2006Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Hiroyuki Akatsu, Rama Divakaruni, Marwan Khater, Christopher M. Schnabel, William Tonti
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Publication number: 20080157202Abstract: Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, Toshiharu Furukawa, Charles Koburger, Jack A. Mandelman, William Tonti
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Publication number: 20080079172Abstract: A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.Type: ApplicationFiled: November 14, 2007Publication date: April 3, 2008Applicant: International Business Machines CorporationInventors: Louis Hsu, Jack Mandelman, William Tonti, Chih-Chao Yang
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Patent number: 7348280Abstract: A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.Type: GrantFiled: November 3, 2005Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Tonti, Chih-Chao Yang