Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: The present invention systems and methods facilitate secure communication of information between devices. A present invention system and method can enable secure communication of proprietary content in a HDCP compliant configuration. In one embodiment, a high definition content protection key secure management method is utilized to enable efficient and secure storage of a HDCP key. A high definition content protection key value is received. The high definition content protection key is encrypted utilizing a secure key value, wherein the secure key value is not accessible via an external port. In one exemplary implementation, the secure key is stored in fuses included in a processing unit. The results of said encrypting in a memory (e.g., a BIOS memory, flash memory, etc.).

Abstract: A notebook computer includes a lower notebook portion that provides a fanless environment having a keyboard and supplemental electronics. Additionally, the notebook computer also includes an upper notebook portion that provides an additional fanless environment having a display and a processing unit, wherein the processing unit includes a general purpose CPU and an integrated GPU configured to operate in the additional fanless environment. Another notebook computer includes a fanless lower notebook body that has a keyboard and a discrete GPU and a fanless upper notebook body that has a display and a general purpose CPU with an integrated GPU, wherein the discrete GPU is configured to augment the integrated GPU. A method of manufacturing a notebook computer is also provided.

Abstract: Circuits, methods, and apparatus that provide transactions to wake an external device from a low-power state before a data transfer. This prevents an interruption that would be caused if the external device exited the low-power state during the data transfer. One example monitors a need for data by a first device. At a predetermined time before data is needed, the first device sends a transaction to a second device. The transaction is intended to wake the second device from a low-power state. If the first device has information to indicate that the second device is not in a low-power state, this transaction can be skipped. The first device then requests data. Later transactions to the second device do not result in the second device exiting the low-power state and therefore do not interrupt or cause delays in the data transfer.

Abstract: The present invention systems and methods facilitate secure communication of information between devices. A present invention system and method can enable secure communication of proprietary content in a HDCP compliant configuration. In one embodiment, a high definition content protection key secure management method is utilized to enable efficient and secure storage of a HDCP key. A high definition content protection key value is received. The high definition content protection key is encrypted utilizing a secure key value, wherein the secure key value is not accessible via an external port. In one exemplary implementation, the secure key is stored in fuses included in a processing unit. The results of said encrypting in a memory (e.g., a BIOS memory, flash memory, etc.).

Abstract: The present invention pertains to a computer chassis with improved airflow to reduce the occurrence of trapped air pockets and increase heat transfer from components within the chassis. The computer chassis includes a plurality of chambers, wherein each of the chambers is separated by a partition. The partitions are operable to reduce the occurrence of trapped air pockets and increase heat transfer from components of the chassis by causing air to flow through each of the chambers. The computer chassis further includes at least two air vents, wherein each of the chambers is coupled to at least one of the at least two air vents through which air enters the chamber, and wherein each of the chambers is coupled to at least one of the at least two air vents through which air exits the chamber.

Abstract: A computer system that employs Peripheral Component Interconnect Express (PCIe) links includes devices that generate a PCIe packet having a header portion that is smaller than the header portion for a conventional PCI packet. The devices may be an endpoint device, such as a graphics processor, and a chipset, such as a root-complex. The reduced size header improves the bus throughput efficiency of the computer system and reduces power requirements for the computer system.

Abstract: Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.