Patents by Inventor William U. Liu
William U. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020013932Abstract: A continuous parametric model is provided for a physical circuit element that includes a base model which exhibits a discontinuity over an allowable range of model parameters or a discontinuity in the first derivative of the allowable range of model parameters. At least one compensation function can be provided to remove the discontinuities of the base model over the allowable range of parametric values and at least one compensation constant can be included to prevent a first derivative of the base model from exhibiting discontinuities over the allowable range of parameters, whereby the base model is rendered continuous. The resulting continuous parametric model provides enhanced simulation/analysis performance when compared to traditional smoothing functions.Type: ApplicationFiled: January 4, 2001Publication date: January 31, 2002Inventors: William U. Liu, Mi-Chang Chang
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Patent number: 6187641Abstract: A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).Type: GrantFiled: December 3, 1998Date of Patent: February 13, 2001Assignee: Texas Instruments IncorporatedInventors: Mark S. Rodder, William U. Liu
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Patent number: 6159816Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.Type: GrantFiled: June 7, 1995Date of Patent: December 12, 2000Assignee: TriQuint Semiconductor Texas, Inc.Inventors: Darrell G. Hill, Timothy S. Henderson, William U. Liu, Shou-Kong Fan, Hin-Fai Chau, Damian Costa, Ali Khatibzadeh
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Patent number: 6124627Abstract: A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).Type: GrantFiled: June 17, 1999Date of Patent: September 26, 2000Assignee: Texas Instruments IncorporatedInventors: Mark S. Rodder, William U. Liu
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Patent number: 5702958Abstract: The invention described herein includes, in one of its forms, a method for fabricating a semiconductor device having ledge material (148, 150, 152, 162) extending over an undercut region. The method comprises the step of forming a layer of material 164 in tensile stress over the undercut region, or region to be undercut. The layer of material in tensile stress can be a dielectric, such as silicon nitride, and provides support for the ledge material in subsequent processing steps.Type: GrantFiled: August 9, 1994Date of Patent: December 30, 1997Assignee: Texas Instruments IncorporatedInventors: William U. Liu, Darrell G. Hill
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Patent number: 5616950Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.Type: GrantFiled: June 7, 1995Date of Patent: April 1, 1997Assignee: Texas Instruments IncorporatedInventor: William U. Liu
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Patent number: 5571732Abstract: In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.Type: GrantFiled: June 7, 1995Date of Patent: November 5, 1996Assignee: Texas Instruments IncorporatedInventor: William U. Liu
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Patent number: 5552617Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.Type: GrantFiled: August 16, 1995Date of Patent: September 3, 1996Assignee: Texas Instruments IncorporatedInventors: Darrell G. Hill, Timothy S. Henderson, William U. Liu, Shou-Kong Fan, Hin-Fai Chau, Damian Costa, Ali Khatibzadeh
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Patent number: 5525817Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.Type: GrantFiled: September 20, 1993Date of Patent: June 11, 1996Assignee: Texas Instruments IncorporatedInventors: Darrell G. Hill, William U. Liu
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Patent number: 5455440Abstract: Generally, and in one form of the invention, a method is disclosed for reducing base-to-emitter leakage in a bipolar transistor having an active region 22 bounded by an isolation implant boundary 24, said method comprising arranging an emitter contact 26 and a base contact 36 such that at a crossing of the contacts over the implant boundary, a leakage current between the contacts along the boundary is limited by a necessity to transit the thickness of a layer of material, and whereby said transistor exhibits improved gain, noise performance, and reliability.Type: GrantFiled: May 17, 1994Date of Patent: October 3, 1995Assignee: Texas Instruments IncorporatedInventors: Timothy S. Henderson, Shou-kong Fan, William U. Liu
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Patent number: 5330932Abstract: In one form of the invention, a method is disclosed for removing portions of successive layers of GaAs 34 and GaInP 32 comprising the steps of: performing an anisotropic reactive ion etch on the GaAs layer; and performing an isotropic wet etch on the GaInP layer, whereby a mesa formed as a result of the reactive ion etch and the wet etch has substantially vertical sidewalls, and further whereby GaInP/GaAs structures having dimensions of less than approximately 3.0 .mu.m may be fabricated.Type: GrantFiled: December 31, 1992Date of Patent: July 19, 1994Assignee: Texas Instruments IncorporatedInventors: William U. Liu, Shou-Kong Fan, Timothy S. Henderson, Darrell G. Hill
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Patent number: 5278083Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.Type: GrantFiled: October 16, 1992Date of Patent: January 11, 1994Assignee: Texas Instruments IncorporatedInventors: Darrell G. Hill, William U. Liu
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Patent number: 5270223Abstract: Generally, and in one form of the invention, a multiple layer wide bandgap collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14.Other devices, systems and methods are also disclosed.Type: GrantFiled: June 28, 1991Date of Patent: December 14, 1993Assignee: Texas Instruments IncorporatedInventor: William U. Liu
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Patent number: 5171697Abstract: Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14.Type: GrantFiled: June 28, 1991Date of Patent: December 15, 1992Assignee: Texas Instruments IncorporatedInventors: William U. Liu, Darrell G. Hill