Patents by Inventor William V. Huott
William V. Huott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7129764Abstract: A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate. The state machine includes state elements and associated logic. The associated logic is configured to allow said state elements to pass through a number of logic states for every same number of consecutive edges of the global clock when the associated logic is enabled. The number is a positive integer.Type: GrantFiled: February 11, 2005Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: William V. Huott, Timothy G. McNamara
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Patent number: 6912665Abstract: A test methodology is used to conduct an automatic chip timing analysis in coarse and fine resolution steps. Timing adjustment circuits implement coarse timing adjustment and fine timing adjustment for chip timing analysis. Timings such as clock, address and control inputs to a memory system can be digitally adjusted with respect to each other. A timer circuit is provided with a counter so that an incremental or decremental timing analysis can be carried out with a specific timing step. An algorithm is implemented which provides an effective, low-cost and accurate timing analysis. A nested loop is set up in the BIST where all possibilities of timing relationships between two or more signals can be applied to a device under test, and weaknesses, or failing timing conditions, can be found.Type: GrantFiled: April 5, 2001Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Wayne F. Ellis, John A. Fifield, Louis Hsu, William V. Huott
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Patent number: 6865501Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.Type: GrantFiled: October 30, 2003Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Leendert M. Huisman, William V. Huott, Franco Motika, Leah M. Pfeifer Pastel
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Patent number: 6836865Abstract: A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.Type: GrantFiled: October 9, 2001Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Mary P. Kusko, William V. Huott, Bryan J. Robbins, Timothy Charest
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Publication number: 20040230882Abstract: Pseudo-Random Controls are added to an LBIST design which allow for the system clock sequence, scan (A/B) clock sequence, PRPG weighting and PRPG clock gating to vary during the LBIST test. An LFSR is added to the LBIST control logic to generate pseudo-random data that is multiplexed with the existing fixed value control parameters. Weight logic is also added to the LFSR output which gives certain control parameter settings a higher probability of occuring during the LBIST test.Type: ApplicationFiled: May 12, 2003Publication date: November 18, 2004Applicant: International Business Machines CorporationInventors: William V. Huott, Timothy J. Koprowski, Peilin Song
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Publication number: 20040093185Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.Type: ApplicationFiled: October 30, 2003Publication date: May 13, 2004Applicant: International Business Machines CorporationInventors: Leendert M. Huisman, William V. Huott, Franco Motika, Leah M. Pfeifer Pastel
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Patent number: 6671644Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.Type: GrantFiled: August 15, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Leendert M. Huisman, William V. Huott, Franco Motika, Leah M. Pfeifer Pastel
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Patent number: 6662324Abstract: The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function.Type: GrantFiled: August 21, 2000Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Franco Motika, Richard F. Rizzolo, Peilin Song, William V. Huott, Ulrich Baur
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Patent number: 6629281Abstract: This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.Type: GrantFiled: September 26, 2000Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Timothy G. McNamara, William V. Huott, Timothy J. Koprowski
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Patent number: 6629280Abstract: An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.Type: GrantFiled: September 25, 2000Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Timothy J. Koprowski, William V. Huott, Timothy G. McNamara, Pradip Patel
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Patent number: 6625769Abstract: A method is provided for analyzing the functionality of an integrated circuit (IC). The method includes the step of applying a built-in self test (BIST) to the integrated circuit. The BIST includes a plurality of tests that result in the integrated circuit passing and/or failing with respect to predefined criteria. During the applying step, a substrate current of the integrated circuit is measured and analyzed as a function of at least one variable. Also during the applying step, optical emissions of the integrated circuit are measured and analyzed. Defects in the functionality of the integrated circuit are identified, based on at least one of the substrate current and the optical emissions.Type: GrantFiled: November 1, 2000Date of Patent: September 23, 2003Assignee: International Business Machines CorporationInventors: William V. Huott, Moyra K. Mc Manus, Pia Naoko Sanda
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Publication number: 20030070127Abstract: A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Inventors: Mary P. Kusko, William V. Huott, Bryan J. Robbins, Timothy Charest
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Publication number: 20030036869Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.Type: ApplicationFiled: August 15, 2001Publication date: February 20, 2003Applicant: International Business Machines CorporationInventors: Leendert M. Huisman, William V. Huott, Franco Motika, Leah M. Pfeifer Pastel
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Publication number: 20020194539Abstract: A test methodology is used to conduct an automatic chip timing analysis in coarse and fine resolution steps. Timing adjustment circuits implement coarse timing adjustment and fine timing adjustment for chip timing analysis. Timings such as clock, address and control inputs to a memory system can be digitally adjusted with respect to each other. A timer circuit is provided with a counter so that an incremental or decremental timing analysis can be carried out with a specific timing step. An algorithm is implemented which provides an effective, low-cost and accurate timing analysis. A nested loop is set up in the BIST where all possibilities of timing relationships between two or more signals can be applied to a device under test, and weaknesses, or failing timing conditions, can be found.Type: ApplicationFiled: April 5, 2001Publication date: December 19, 2002Applicant: International Business Machines CorporationInventors: Wayne F. Ellis, John A. Fifield, Louis Hsu, William V. Huott
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Patent number: 6314540Abstract: A partitioned pseudo-random logic test (PRLT) for integrated circuit chips for improving manufacturability is disclosed. The technique makes available previously difficult-to-collect empirical data to accurately improve test effectiveness while significantly lowering test time and test cost. An embodiment includes a method for testing IC chips, including generating values for latches for a complete test pattern set, partitioning the test pattern set into a plurality of partitioned test pattern subsets, and running the subsets against a chip. Another embodiment is directed to a system that tests IC chips, having a latch value generator that generates values for latches for a complete test pattern set, a test pattern divider that partitions the complete test pattern set into a plurality of partitioned test pattern subsets, and a tester that runs the partitioned test pattern subsets against the chip.Type: GrantFiled: April 12, 1999Date of Patent: November 6, 2001Assignee: International Business Machines CorporationInventors: William V. Huott, Mary P. Kusko, Gregory O'Malley, Bryan J. Robbins
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Patent number: 6311311Abstract: A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to generate a signature of all updates to multiple architected registers. Single instructions update multiple registers across multiple machine cycles, and an accumulation register allows order independence of partial results. A register update consists of the data to be written, an address identifying which register is to be updated, and controls to identify if this is the last register update that will be done by the current instruction. For each cycle, logic evaluates the update controls to select what will be gated into the accumulation register and also sets MISR control latches to tell how to update the MISR the next cycle. The latched MISR controls select whether the MISR will clear, hold, or evaluate.Type: GrantFiled: August 19, 1999Date of Patent: October 30, 2001Assignee: International Business Machines CorporationInventors: Scott B. Swaney, William V. Huott, Bruce Wile
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Patent number: 6125465Abstract: A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.Type: GrantFiled: January 9, 1998Date of Patent: September 26, 2000Assignee: International Business Machines CorporationInventors: Timothy G. McNamara, William V. Huott, Timothy J. Koprowski
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Patent number: 5633877Abstract: An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.Type: GrantFiled: May 31, 1995Date of Patent: May 27, 1997Assignee: International Business Machines CorporationInventors: Philip G. Shephard, III, William V. Huott, Paul R. Turgeon, Robert W. Berry, Jr., Gulsun Yasar, Frederick J. Cox, Pradip Patel, Joseph B. Hanley, III
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Patent number: 5420467Abstract: A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies.Type: GrantFiled: January 31, 1992Date of Patent: May 30, 1995Assignee: International Business Machines CorporationInventors: William V. Huott, Timothy G. McNamara