Abstract: A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.

Abstract: Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.

Abstract: Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. One edge detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein.

Abstract: Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.

Abstract: Circuits for improving efficiency and performance of processor-memory transactions are disclosed. One such system includes a processor having a first bus interface unit and a second bus interface unit. The processor can initiate more than one concurrent pending transaction with a memory. Also disclosed are methods for incorporating or utilizing the disclosed circuits.

Abstract: Systems and methods are disclosed for locking code in cache. In one embodiment, a processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each cache way is further divided into a number of cache way portions. The cache controller is configured to utilize a first signal and a second signal. The first signal designates one of the cache ways as a partial cache way and the second signal defines which ones of the cache way portions of the partial cache way are to be locked.

Abstract: Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. One edge detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein.

Abstract: A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.

Abstract: A processor disclosed herein comprises a clock configured to drive clock signals and a processor pipeline having a plurality of stages. The processor includes processor idling circuitry, which is configured within the stages and is responsive to an idle_request signal. A first stage comprises a device for stopping incoming instruction values from being further processed when the idle_request signal is received. Also, at least two of the remaining stages comprise idle_flag logic configured to receive the idle_request signal, the idle_flag logic further configured to transmit an idle_flag through the processor pipeline.

Abstract: An improved program status register is disclosed with a feature to handle state change for a processor and its memory subsystem. The program status register comprises a clock, at least one update value for updating the program status register to a second value from a first value when an update enable signal is received, a sampled program status register storing the first value of the program status register, and a state change sampling register generating a synchronized state change signal from a state change indication signal and the clock. When the update enable signal is initially received and a state change indication signal is further received thereafter during a first clock cycle, an updated output of the program status register is restored through a first selection module triggered by the synchronized state change signal to the first value in a second clock cycle following the first clock cycle.

Abstract: A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with the tag array, a tag read control logic module for controlling a tag array search, a comparator associated with the tag array, and a storage module for storing a match result of the comparator while processing a first memory access request that accesses a first data address in a first cacheline of the data array. The stored match result is used for a second memory access request that intends to access a second data address sequential to the first data address, thereby avoiding searching the tag array for the second memory access request.

Abstract: The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.

Abstract: A processor and method for handling out-of-order instructions is provided. In one embodiment, the processor comprises instruction pre-fetch logic configured to pre-fetch instructions from memory. The processor further comprises instruction information logic configured to store information about instructions fetched from memory. The processor further comprises control logic configured to control temporary storage of the information related to a pre-fetched instruction if there is currently an active memory access and the currently pre-fetched instruction is an out-of-order instruction. The method pre-fetches the out-of-order in instruction, temporarily stores information associated with the out-of-order instruction in a storage location, and if the memory access completes without encountering a data fault, then saves the temporarily stored information and processes the pre-fetched instruction.

Abstract: A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.

Abstract: A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with the tag array, a tag read control logic module for controlling a tag array search, a comparator associated with the tag array, and a storage module for storing a match result of the comparator while processing a first memory access request that accesses a first data address in a first cacheline of the data array. The stored match result is used for a second memory access request that intends to access a second data address sequential to the first data address, thereby avoiding searching the tag array for the second memory access request.

Abstract: A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions.

Abstract: A reflexively scaling memory bus interface system and method allows the implementation of an ISA bus peripheral card that will effectively operate within the decoded memory space of another sixteen bit card while using only the external memory components required for an eight bit interface. The same peripheral card will also be compatible in a system with other eight bit cards located in a corresponding memory space. The reflexively sizing memory bus interface responds automatically to memory accesses that vary in data bus width (i.e., eight or sixteen bits) by directly or indirectly monitoring feedback signals from other devices on the bus. This technique solves the problem of integrating eight and sixteen bit cards on the ISA bus.

Abstract: Cattle and other livestock are protected from insects such as face flies, horn flies, ticks and the like by use of a uniquely effective insect control device attached to the animal. The insect control device comprises a polymeric resin matrix, preferably in the form of an ear tag or ear band, containing a liquid, insecticidally-active isomer of alpha-cyano-3-phenoxy-benzyl-alpha-isopropyl-4-chlorophenyl acetate.