Patents by Inventor William VANDENDAELE

William VANDENDAELE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11761920
    Abstract: A method of estimating a nitrogen site carbon concentration, in a first epitaxial layer made of carbon-doped gallium nitride of an electronic component, including steps of: estimating an electric capacitance of a stack interposed between the first layer and a first electrode of the component; heating the component; measuring an offset of a threshold voltage of the component; and deducing therefrom a nitrogen site carbon surface concentration in the first layer.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: September 19, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Abygael Viey, Marie-Anne Jaud, William Vandendaele
  • Patent number: 11656267
    Abstract: A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 23, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Abygael Viey, William Vandendaele, Jacques Cluzel, Jean Coignus
  • Publication number: 20220299559
    Abstract: A method for determining a CET mapping characterizing the capture and emission time of traps in a transistor for a given stress voltage and a given temperature, called an optimal CET mapping, this determination being made from an experimental measurement of the time course of the change in the threshold voltage V_TH for the same stress voltage and the same temperature and from a distribution function of the traps, the distribution function may be defined by N_par parameters. More particularly, the method implements a genetic algorithm whose parameters are regularly updated in order to optimize the computation time while decreasing the risk of reaching a local minimum in the determination of the optimal CET mapping.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 22, 2022
    Inventors: Abygael VIEY, Xavier GARROS, Louis GERRER, William VANDENDAELE
  • Publication number: 20210302487
    Abstract: A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Abygael Viey, William Vandendaele, Jacques Cluzel, Jean Coignus
  • Publication number: 20210156812
    Abstract: A method of estimating a nitrogen site carbon concentration, in a first epitaxial layer made of carbon-doped gallium nitride of an electronic component, including steps of: estimating an electric capacitance of a stack interposed between the first layer and a first electrode of the component; heating the component; measuring an offset of a threshold voltage of the component; and deducing therefrom a nitrogen site carbon surface concentration in the first layer.
    Type: Application
    Filed: November 10, 2020
    Publication date: May 27, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux l'Énergies Alternatives
    Inventors: Abygael Viey, Marie-Anne Jaud, William Vandendaele
  • Publication number: 20190271736
    Abstract: The invention relates to a characterization device for a power diode including: first and second power supply nodes; a power supply (including a first voltage source connected to the first node; a second voltage source; a first resistor connected in series between the second voltage source and said second node; and a controlled switch for selectively connecting the second node to a potential lower than a first potential); and a voltage clipping circuit (including a third voltage source; a second resistor and a first diode connected in series between the third voltage source and said second node; and a measurement terminal, connected to an intermediate node between the second resistor and the first diode).
    Type: Application
    Filed: November 6, 2017
    Publication date: September 5, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: William VANDENDAELE, Thomas LORIN
  • Publication number: 20130256689
    Abstract: The invention concerns an optoelectronic semiconductor structure (100) including a semiconductor substrate (110) including a first face (111), a nucleation layer (120) and a nanowire (160) in contact with the nucleation layer. The nucleation layer (120) covers a portion of the first face (111) which is called the “nucleation” face, and where the portion (114) of the first face (111) not covered by the nucleation layer (120) is called the “free” portion. The structure also includes a conducting layer (141) in contact with the free portion (114) of the substrate (110), where the said conducting layer is also in contact with the nanowire over the perimeter of the nanowire (160). The invention also concerns a method of manufacture of such a structure (100).
    Type: Application
    Filed: March 27, 2013
    Publication date: October 3, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Emilie POUGEOISE, Anne-Laure BAVENCOVE, William VANDENDAELE