Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending output data to a second MISR. The method includes determining a first seed signature value associated with the first MISR that induces the first MISR to have a first final signature value comprising a plurality of identical binary values when the first set of devices send valid output data to the first MISR when receiving a first predetermined sequence of input data.

Abstract: A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

Abstract: An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

Abstract: An existing trace array on a chip is used to store the locations of bit failures from the automatic self-testing of an SRAM array. If a system is having problems, a technician can trigger the automatic test and then scan the trace array, thereby locating a large number of errors on the SRAM array very quickly.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.

Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test system). The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be used with dual logical views to reduce test time. The ABIST generates pseudo-random address patterns for improved test coverage. A jump-to-third pointer control command enables branching to perform looping after a background has been filled. A data register is divided into multiple sections to enable a Walking/Marching pattern to be executed individually and concurrently in the dual views to further reduce test times.

Abstract: Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.