Patents by Inventor William W. Chen

William W. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145034
    Abstract: The present application provides, in some aspects, methods of identifying a condensate of interest associated with a el disease. Also provided are methods of identifying a marker for identifying a condensate of interest associated with a disease. In other aspects, provided herein are methods of identifying a therapeutic agent useful for treating a disease via the identified condensate of interest.
    Type: Application
    Filed: March 1, 2022
    Publication date: May 2, 2024
    Inventors: William W. CHEN, John C. MANTEIGA, Violeta YU, Ann D. KWONG, Peter Jeffrey DANDLIKER, Bruce Aaron BEUTEL, Chi ZHANG, Lingyao ZENG, Andreas STEFFEN, Daniel Franz FREITAG
  • Patent number: 11948226
    Abstract: A computer-implemented method for clinical workspace simulation includes capturing a real-world environment by an imaging device of an augmented reality headset and generating a composite view by rendering a first virtual object relative to a surgical table in the real-world environment. Captured real-world environment and the rendered first virtual object are combined in the composite view, which is displayed on a display of the augmented reality headset worn by a user.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: April 2, 2024
    Assignee: COVIDIEN LP
    Inventors: Max L. Balter, Michael A. Eiden, William J. Peine, Unnas W. Hussain, Justin R. Chen
  • Patent number: 8525313
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 3, 2013
    Assignee: Semtech Corporation
    Inventors: Binneg Y. Lao, William W. Chen
  • Publication number: 20120261384
    Abstract: An interrupter system for a switchgear. The interrupter system includes a source-side conductor, a load side conductor, and an interrupter. A source-side voltage detector is positioned proximate to the source-side conductor and a load-side voltage detector is positioned proximate to the load-side conductor. An insulating overmold encases both conductors, both voltage detectors, and the interrupter. A controller is coupled to both of the detectors and is configured to detect a source-side voltage and a load-side voltage.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 18, 2012
    Inventors: Mike LaBianco, William W. Chen, Nenad Uzelac
  • Publication number: 20120168928
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: SEMTECH CORPORATION
    Inventors: Binneg Y. LAO, William W. Chen
  • Patent number: 8159052
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: April 17, 2012
    Assignee: Semtech Corporation
    Inventors: Binneg Y. Lao, William W. Chen
  • Publication number: 20090256266
    Abstract: A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.
    Type: Application
    Filed: July 1, 2008
    Publication date: October 15, 2009
    Applicant: SIERRA MONOLITHICS, INC.
    Inventors: Binneg Y. LAO, William W. Chen
  • Patent number: 6803252
    Abstract: Methods and apparatus for providing connection packages for high-speed integrated circuits (“ICs”) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density IC's input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: October 12, 2004
    Assignee: Sierra Monolithics, Inc.
    Inventors: Binneg Y. Lao, William W. Chen, David A. Rowe, Inho Kim
  • Publication number: 20030095014
    Abstract: Connection packages for high-speed integrated circuits (“ICs”) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density IC's input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced. A portion of the coupled microstrips near the IC pads can be widened to increase the capacitance so that the overall transmission path can become an all-pass network—from the IC pads, through the bonding wires, to the microstrips.
    Type: Application
    Filed: November 21, 2001
    Publication date: May 22, 2003
    Inventors: Binneg Y. Lao, William W. Chen, David A. Rowe
  • Publication number: 20030096447
    Abstract: Methods and apparatus for providing connection packages for high-speed integrated circuits (“ICs”) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density IC's input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced. A portion of the coupled microstrips near the IC pads can be widened to increase the capacitance so that the overall transmission path can become an all-pass network—from the IC pads, through the bonding wires, to the microstrips.
    Type: Application
    Filed: November 21, 2001
    Publication date: May 22, 2003
    Inventors: Binneg Y. Lao, William W. Chen, David A. Rowe, Inho Kim
  • Patent number: 6560085
    Abstract: An apparatus and method for interrupting the flow of electrical current in a line is disclosed. The invention provides for better limitation of current than can be achieved in the prior art. With effective current limitation, the magnetic force generated by the circuit breaker coil will not be excessive thereby reducing potential damage to the circuit breaker armature, increasing the interruption rating of the circuit breaker and end-use equipment and decreasing the interruption pressure within the circuit breaker.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 6, 2003
    Assignee: Square D Company
    Inventors: William W. Chen, Randall L. Siebels, Steven C. Wilgenbusch
  • Publication number: 20020196592
    Abstract: The present invention provides a transformer having a positive temperature coefficient resistivity polymer element electrically coupled to either the primary or secondary winding of the transformer to provide protection against overcurrent, short circuit and thermal overheating conditions. Use of the positive temperature coefficient resistivity polymer element helps to further reduce the amount of space needed for electrical and thermal protection of the transformer while lowering manufacturing costs by eliminating the use of a fuse and fuse block. The positive temperature coefficient resistivity polymer element also provides an advantage to the end user in that the positive temperature coefficient resistivity polymer element does not require replacement, unlike prior art fuses, following an overcurrent, short circuit or thermal overheating event.
    Type: Application
    Filed: June 20, 2001
    Publication date: December 26, 2002
    Inventors: William W. Chen, Gary T. Jones, Jay B. Ballard, E. J. Homier
  • Patent number: 6313723
    Abstract: A circuit breaker and method for interrupting the flow of electric current in a line having a load and a source including a first switch connected in series with the line and a first actuating device coupled to the first switch and adapted to be actuated by at least one activating signal, to move the first switch from the closed position to the open position. A resistor having a positive temperature coefficient of resistivity is connected in series with the first switch and a voltage limiting device is connected in parallel with the resistor. A second actuating device is coupled to the first switch and is adapted to be actuated by at least one remote control activating signal, to move the first switch to the open position or to the closed position. The second actuating device further includes a coil and a second switch connected to the coil and to the line, the second switch adapted for activating the coil upon the receipt of the remote control activating signal.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: November 6, 2001
    Assignee: Square D Company
    Inventors: William W. Chen, Bruce F. Lindholm
  • Patent number: 6072673
    Abstract: A medium to high voltage load circuit interrupter and method for breaking the flow of electric current in a line having a load and a source. A main switch is connected in series with the line. A metal resistor having a positive temperature coefficient of resistivity (PTC element) is connected in series to the arcing switch, wherein the metal resistor and arcing switch are connected in parallel with the main switch. The main switch moves from the closed position to the open position prior to the arcing switch moving from the closed position to the open position. The circuit interrupter further includes an arc chute having a channel and electrically coupled to the arcing switch wherein the arcing switch is positioned within the channel when the arcing switch is in a closed position. In one embodiment, the PTC element is positioned on an insulator positioned between a ground and the main switch and an arcing switch. In another embodiment, the PTC element is positioned within a channel in the arc chute.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: June 6, 2000
    Assignee: Square D Company
    Inventors: William W. Chen, Eldridge Byron, Stanley J. Brooks, Lori Dorrell, Gary W. Scott
  • Patent number: 6045728
    Abstract: An erosion-resistant, chemically vapor-deposited zinc sulfide window and method of making the same are disclosed. The method includes the step of immersing a chemically vapor-deposited or a hot isostatic pressed, chemically vapor-deposited zinc sulfide body into a liquid comprising gallium, the liquid having a temperature of about 600.degree. C. to about 1000.degree. C., for at least about thirty minutes to form a gallium-doped body. The gallium-doped, chemically vapor-deposited zinc sulfide body according to the invention is one capable of transmitting light having a wavelength in the range of about 300 nanometers to about 15,000 nanometers. Furthermore, the gallium-doped, chemically vapor-deposited zinc sulfide window according to the invention is capable of transmitting light, having a wavelength in the range of about 380 nanometers to about 700 nanometers have been exposed to rain erosion for 20 minutes at 470 miles per hour with a 90.degree.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: April 4, 2000
    Assignee: Raytheon Company
    Inventors: William W. Chen, Norman H. Harris, Stephen A. Gabelich
  • Patent number: 6020802
    Abstract: A circuit breaker for interrupting the flow of electric current in a line includes a switch connected in series with the line, the switch having an open position and a closed position. At least one positive temperature coefficient resistivity element (PTC element) is connected in series with the line. A first magnetic coil is positioned around a yoke, for example, an iron core, and connected in parallel with the PTC element and a second magnetic coil is positioned around the yoke and connected in series with the line and the switch. A voltage limiting device, such as a metal oxide varistor, is connected in parallel with the at least one PTC element. An armature is pivotally mounted in relation to the yoke wherein the yoke and the armature form a magnetic circuit with the first magnetic coil and the second magnetic coil.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: February 1, 2000
    Assignee: Square D Company
    Inventors: Brett E. Larson, William W. Chen
  • Patent number: 5999384
    Abstract: A circuit protection apparatus employs a PTC element for overload and/or short circuit protection and an arcing fault interruption arrangement. The circuit protection apparatus may be employed in a ground fault receptacle for interrupting the flow of electrical current in a line in response to any of a plurality of different types of fault conditions on the line. The circuit protection apparatus may include a set of contacts connected in series with the line, and having an open position and a closed position, a trip device coupled to the contacts, adapted to be actuated by a trip signal, to move the contacts from the closed position to the open position and an element having a positive temperature coefficient of resistivity (PTC) connected in series with the contacts. The PTC element is connected to the trip device to provide the trip signal to the device in response to overload or short circuit conditions in the line.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: December 7, 1999
    Assignee: Square D Company
    Inventors: William W. Chen, Andy A. Haun, George D. Gregory, Gary W. Scott
  • Patent number: 5942343
    Abstract: A large, monolithic sapphire structure for use in mid-IR military applications, such as, for example, a window or screen for radar detection equipment. The structure is made by bonding together two or more smaller sapphire panes by a method including the steps of coating a surface of each of the panes with a magnesia vapor and contacting the magnesia-coated surfaces with each other in the presence of a hydrogen-containing gas at a temperature (e.g., about 1500.degree. C. and 2000.degree. C.) and for a time period (e.g., about 45 minutes to about ten hours) sufficient to form a continuous magnesia-alumina spinel interlayer bond between the panes.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: August 24, 1999
    Assignee: Raytheon Company
    Inventor: William W. Chen
  • Patent number: 5933311
    Abstract: A circuit breaker including a switch having an open and a closed position connected to a line of the circuit breaker. A first actuating device, actuated by a first activating signal, is connected to the switch to move the switch from the closed position to the open position wherein the flow of electric current in the line is interrupted. A positive temperature coefficient resistivity element (PTC element) is tripped at least once wherein the tolerance of the PTC element is reduced and the PTC element is connected to the first actuating device for providing the first activating signal. In another embodiment of the present invention, a second actuating device, actuated by a second activating signal provided by the circuit breaker current, is connected to the switch to move the switch from the closed position to the open position wherein the flow of electric current in the line is interrupted.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: August 3, 1999
    Assignee: Square D Company
    Inventors: William W. Chen, Brett E. Larson
  • Patent number: 5771567
    Abstract: Methods of fabricating a porous ceramic composite having voltage-variable dielectric properties. The composite is made as follows. A polycrystalline ferroelectric powder, which is a ferroelectric perovskite such as barium strontium titanate, for example, is provided. The powder, a binder and a filler are then mixed in water to form a slurry. The powder-binder-filler slurry is then dried. The dried powder-binder-filler slurry is granulated. The granulated powder-binder-filler is pressed into a die. The binder and filler are then burned out to form a fragile porous ash-like structure. The porous structure is then sintered to form porous ceramic parts. The porous ceramic parts are then machined tiles. The machined porous tiles may then be tested for microwave properties. Fabrication methods for producing porous ferroelectric ceramic-polymer composite tiles or subaperture blanks and continuous transverse stub electronically scanned antenna plates or subapertures are also disclosed.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: June 30, 1998
    Assignee: Raytheon Company
    Inventors: Brian M. Pierce, Norman H. Harris, Thomas Kirk Dougherty, William W. Chen, Florentino V. Lee