Abstract: A current switching cell for a digital to analog converter. The switching cell includes three stages, a first control stage, a data stage, and a second control stage. The first control stage is configured to either disconnect the outputs of the digital to analog converter, or to connect them to the outputs of the data stage. The data stage is configured to operate in one of two states, depending on a data signal received, and the second control stage is configured to selectively invert the output of the digital to analog converter. The two control stages may be driven with several combinations of control waveforms to implement a non return to zero mode, a return to zero mode, inverse non return to zero mode, and inverse return to zero mode.

Abstract: A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Abstract: A current switch. The novel current switch includes a differential pair of transistors Q1 and Q2, a pair of cascode transistors QA and QB coupled to Q1 and Q2, respectively, and a circuit for maintaining QA and QB in an ‘on’ state regardless of the states of Q1 and Q2. The circuit for keeping QA and QB on includes first and second current sources adapted to supply first and second trickle currents to the emitters of QA and QB, respectively. The bases of QA and QB are connected in common to a voltage source VREF4, which, in an illustrative embodiment, is implemented using a Schottky diode for lower impedance. The circuit for driving Q1 and Q2 may also be implemented using a current switch with trickle current, cascode transistors Q14 and Q15 to further improve settling times.

Abstract: An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) (10) with a novel active offset method for comparators. The novel ADC architecture (10) includes a first circuit (12, 14) for receiving an input signal; a second circuit (18) for setting a predetermined number of thresholds using a predetermined number of preamplifiers (60) with weighted unit current sources (66) in each of the preamplifier outputs; and a third circuit (20) for comparing the input to the thresholds. In the preferred embodiment, the ADC (10) includes trimmable current sources (66). The ADC (10) of the present invention also includes an improved comparator circuit (62).

Abstract: A high-performance delta sigma analog-to-digital converter. The high-performance delta sigma analog-to-digital converter includes a first mechanism for converting an input analog signal to a digital output signal. The first mechanism is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism compensates for the alteration in the transfer function via a single additional digital-to-analog converter. In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism. The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism includes an additional latch that compensates for the signal dependent jitter delay. The first mechanism includes a resonator and a quantizer. The second mechanism includes a feedback path from an output of the quantizer to the resonator.

Abstract: A continuous time Bandpass Delta Sigma (&Dgr;&Sgr;) Modulator architecture with feedforward and feedback coefficients to completely specify both the signal transfer function (STF) and the noise transfer function (NTF) for a stable modulator ADC system.

Abstract: A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.

Abstract: A sample and hold circuit uses a Class AB amplifier architecture rather than a diode bridge in a sampling gate. Input and output transistor pairs (Q5, Q6; Q7, Q8) receive an input voltage (Vin) and provide at an output terminal (6) (a) an output voltage that tracks the input signal, and (b) a current from a load dependent current source (Vcc, Vee). The output current used to charge a sample holding capacitor (Ch) is not limited to the input standing current, and operates with a lower quiescent power consumption and better distortion than prior circuits. Complementary bipolar transistors (Q15, Q16, Q17, Q18; Q9, Q10, Q11, Q12) are used in a clock driver circuit and in the sampling gate to compensate for the different operating speeds of the npn and pnp transistors.