Abstract: A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

Abstract: A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer dielectric (ILD) located over a semiconductor substrate. Fabricating the interconnect also includes depositing a sacrificial fill material over the surface and in the via opening. Fabricating the interconnect further includes removing the sacrificial fill material from the surface, depositing a poison-blocking-layer over the surface and forming a trench pattern in a photoresist layer formed over the poison-blocking-layer. The poison-blocking-layer is configured to prevent poisons from entering the photoresist layer.

Abstract: The invention provides a semiconductive device that comprises interlevel dielectric layers that are located over devices. The interlevel dielectric layers have a dielectric constant (k) less than about 4.0. Interconnects are formed within or over the interlevel dielectric layers. The semiconductive device further comprises an aluminum oxide barrier located between at least one pair of the interlevel dielectric layers. The aluminum oxide barrier is substantially laterally co-extensive with the interlevel dielectric layers.

Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100. The first etch is designed to be selective to a remaining portion of the hardmask layer 140, 150. A second etch, which is different from the first etch, is conducted on a remaining portion of the hardmask 140, 150, and it is designed to be less selective than the first etch to the remaining portion of the hardmask 140, 150. The first etch allows polymer to build up on the sidewalls of the opening 162, and the polymer substantially remains on the sidewalls during the second etch.

Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an etch-stop layer 140, the dielectric layer having a photoresist layer 170 located thereover and the first etch being selective to the etch-stop layer 140. A second etch different from the first etch is conducted on the etch-stop layer 120, the second etch including nitrogen and at least one fluorocarbon gas, such that the ratio of nitrogen to carbon in the etchant is greater than about 5:1.

Abstract: An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within trench spaces.

Abstract: An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within trench spaces.

Abstract: An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within trench spaces.

Abstract: In one embodiment this is a method of clamping semiconductor wafers for processing with the active face down. The method comprises: supporting a face down wafer 10 on an intermediate support 15; placing a clamping surface 14 at least adjacent to a backside of the wafer; moving at least three bevel-edged pins 11 upward to engage the beveled edges 12 with portions of the periphery of the face to press the wafer 10 against the clamping surface 14; moving the intermediate support 15 away from the wafer 10, and removing photoresist from the wafer by ashing the photoresist, whereby photoresist is essentially completely removed and essentially no unremoved photoresist remains to contaminate later processing.