Patents by Inventor William W. Freitag, Jr.

William W. Freitag, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220414456
    Abstract: The described embodiments include an electronic device having a processor. The processor performs operations for handling watermarks in files. As part of the operations, the processor processes a portion of a file in a classification neural network to determine whether a watermark is present in the portion of the file. Based on a result of the processing, the processor performs an update associated with the watermark in the portion of the file. The processor then provides the updated portion of the file.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Nicholas P. Malaya, William W. Freitag, JR.
  • Patent number: 7088680
    Abstract: A system and method are presented for digital communication via a time division multiplexed serial data stream. A serial communication system according to the present invention includes a serial communication controller having a set of functional units each configured to perform a specific function of a serial communication protocol. The functional units are operably coupled in series in order to produce digital data according to the serial communication protocol. The set of functional units operates alternately upon an active one of the multiple serial data channels within the time division multiplexed serial data stream. Each functional unit may be a state machine including one or more programmable registers for storing state information which determines the operating state of the functional unit.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: August 8, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William W. Freitag, Jr., Daniel B. Reents
  • Patent number: 6237054
    Abstract: A network interface unit is presented including a microcontroller having multiple blocks of programmable logic that are variably configurable to perform selected functions. The network interface unit may be configured to assemble, transmit, and receive data units (i.e., frames) of one communication protocol, then later reconfigured to assemble, transmit, and receive frames of another protocol. The microcontroller includes several components formed upon a single monolithic semiconductor substrate, among them an execution unit. The execution unit includes a processor core and multiple configurable logic blocks (CLBs) coupled to the processor core. The processor core is configured to execute instructions, for example x86 instructions. Each of the multiple CLBs includes programmable logic which may be, for example, PLA circuitry, PAL circuitry, or FPGA circuitry. The programmable logic includes programmable switching elements such as, for example, EPROM elements, EEPROM elements, or SRAM elements.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: May 22, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William W. Freitag, Jr.