Abstract: A current sensing line fault detector includes a unity gain buffer coupling a reference voltage to an IC pin, a current controlled current source coupled to the buffer, a current mode A/D converter developing a digital signal representative of the IC pin current, and logic for determining the state of a transmission line coupled to the IC pin. An alternative current sensing line fault detector includes an OPAMP having a first input coupled to an input node and to a reference current source and having a second input coupled to a reference voltage source. A voltage controlled current source (VCCS) is coupled between the first input of the OPAMP and ground and is controlled by an output of the OPAMP. An A/D converter is coupled to the output of the OPAMP to develop a digital output signal representative of the current flowing through the current sensor.

Abstract: A transimpedance amplifier is configured for high gain, high bandwidth, low noise and stable operation. The transimpedance amplifier includes an amplifier with an output coupled to a load for setting the gain of the amplifier. The input of the amplifier serves as the input to the transimpedance amplifier and is substantially isolated from the load. The input impedance of the transimpedance amplifier is controlled as a function of the applied input signal. Preferably, the amplifier is a field effect transistor (FET). A feedback amplifier is used to control the input impedance. Automatic gain control is used to keep the amplifier out of saturation.

Abstract: An integrated, tuning circuit for tuning a MOSFET-C filter contains a tuning MOSFET and a differential amplifier. A current source is connected to the drain of the tuning MOSFET. The output of the amplifier is coupled to the drain of the tuning MOSFET and to a terminal that connects to the drains of the MOSFETs of the filter, so that the equivalent resistance of the filter is dependant on the current. The current source is coupled to a reference current generator, such that current supplied by the current source to the tuning MOSFET is proportional to the current supplied in the reference current generator, which in turn varies with process and environmental conditions of a capacitance. As a result, changes in process and environmental conditions oppositely affect the capacitance and resistance in the filter, resulting in a fixed RC product and fixed frequency response from the filter.

Abstract: An apparatus for demodulating two pilot tones for use by a servo control for a magnetic read head is disclosed. The apparatus provides positioning information to position the read head adjacent to a desired information track of a magnetic storage medium. The apparatus comprises a first and a second pilot tone demodulation unit. Each pilot tone demodulation unit comprises a band pass filter for providing a first filtered output signal having an amplitude and a phase representative of the first and the second frequency pilot tones, respectively. A delay lock loop receives the first filtered out of the band pass filter and determines a phase of the frequency pilot tone. A multiplier is connected to the output of the band pass filter and the output of the delay lock loop for multiplying the frequency pilot tone with the output signal of the delay lock loop. A low pass filter is connected to the output of the multiplier for filtering out undesired signals and for passing a DC signal.

Abstract: A data separator which extracts data embedded in a read signal includes a delay circuit that is controlled by a frequency synthesizer. The frequency synthesizer provides a write clock during write operations. A controlled oscillator included in the frequency synthesizer resides on a common integrated circuit with the delay circuit. Because component fabrication variations tend to track on a common integrated circuit, the frequency synthesizer compensates for fabrication variations in the delay circuit, thereby producing an accurate delay interval.

Abstract: A data separator for use in extracting data from a read signal includes a restart circuit. The data separator is comprised of a controlled oscillator, a delay circuit, a restart circuit, a phase detector and a data extractor. The delay circuit delays the read signal by an interval approximately equal to the time required to start the controlled oscillator after assertion of the start signal. Accordingly, the oscillator starts in-phase with the delayed read signal. In one embodiment of the present invention, the delay interval of the delay circuit is controlled by a frequency synthesizer which generates a write clock during write operations.

Abstract: A CMOS output buffer interconnects binary logic integrated circuits. The output buffer is readily configurable through variation of a single metallization mask during fabrication for providing interconnection of integrated circuits through either transmission lines or lumped loads. The CMOS output buffer provides a pull-up circuit for pulling an output terminal to a voltage level corresponding to a first logical state and a pull-down circuit for pulling the output terminal to the complementary logical state. The pull-up and pull-down circuits each include a plurality of parallel connectable output drivers. A selected number of output drivers can be connected to the output terminal during fabrication of the integrated circuit through the appropriate metallization mask. The pull-up and pull-down circuits each include a distributed, continuous control electrode providing for delayed propagation of actuation signals.

Abstract: A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N-channel FET connected in parallel between an output terminal and supply terminal V.sub.DD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well as delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.